TMS320DM643 datasheet(91/160 Pages) TI

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AECLKOUTx

ACEx

ABE[7:0]

AEA[22:3]

AED[63:0]

AARE/ASDCAS/ASADS/ASRE(C)

AAOE/ASDRAS/ASOE(C)

AAWE/ASDWE/ASWE(C)

BE1

BE2

BE3

BE4

EA1

EA2

EA3

EA4

The write latency and the length of ACEx assertion are programmable via the SYNCWL and CEEXT fields, respectively, in the EMIFA CE

Space Secondary Control register (CExSEC). In this figure, SYNCWL = 0 and CEEXT = 0.

The following parameters are programmable via the EMIF CE Space Secondary Control register (CExSEC):

− Read latency (SYNCRL): 0-, 1-, 2-, or 3-cycle read latency

− Write latency (SYNCWL): 0-, 1-, 2-, or 3-cycle write latency

− ACEx assertion length (CEEXT): For standard SBSRAM or ZBT SRAM interface, ACEx goes inactive after the final command has

been issued (CEEXT = 0). For synchronous FIFO interface with glue, ACEx is active when ASOE is active (CEEXT = 1).

− Function of ASADS/ASRE (RENEN): For standard SBSRAM or ZBT SRAM interface, ASADS/ASRE acts as ASADS with deselect

cycles(RENEN = 0). For FIFO interface, ASADS/ASRE acts as ASRE with NO deselect cycles (RENEN = 1).

− Synchronization clock (SNCCLK): Synchronized to AECLKOUT1 or AECLKOUT2

AARE/ASDCAS/ASADS/ASRE, AAOE/ASDRAS/ASOE, and AAWE/ASDWE/ASWE operate as ASADS/ASRE, ASOE, and ASWE,

respectively, during programmable synchronous interface accesses.

TMS320DM643

Video/Imaging Fixed-Point Digital Signal Processor

SPRS269A – FEBRUARY 2005 – REVISED APRIL 2005

Figure 5-20. Programmable Synchronous Interface Write Timing for EMIFA (With Write Latency = 0)(A)(B)

DM643 Peripheral Information and Electrical Specifications

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