TMS320DM643 datasheet(120/160 Pages) TI

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5.12.2

McBSP Electrical Data/Timing

TMS320DM643

Video/Imaging Fixed-Point Digital Signal Processor

SPRS269A – FEBRUARY 2005 – REVISED APRIL 2005

5.12.2.1

Multichannel Buffered Serial Port (McBSP) Timing

Table 5-41. Timing Requirements for McBSP

(1) (see Figure 5-46)

–500

–600

NO.

UNIT

MIN

MAX

tc(CKRX)

Cycle time, CLKR/X

CLKR/X ext

4P or 6.67(2)(3)

tw(CKRX)

Pulse duration, CLKR/X high or CLKR/X low

CLKR/X ext

0.5tc(CKRX)– 1(4)

CLKR int

tsu(FRH-CKRL)

Setup time, external FSR high before CLKR low

CLKR ext

1.3

CLKR int

th(CKRL-FRH)

Hold time, external FSR high after CLKR low

CLKR ext

CLKR int

tsu(DRV-CKRL)

Setup time, DR valid before CLKR low

CLKR ext

0.9

CLKR int

th(CKRL-DRV)

Hold time, DR valid after CLKR low

CLKR ext

3.1

CLKX int

tsu(FXH-CKXL)

Setup time, external FSX high before CLKX low

CLKX ext

1.3

CLKX int

th(CKXL-FXH)

Hold time, external FSX high after CLKX low

CLKX ext

(1)

CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also

inverted.

(2)

P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.

(3)

Use whichever value is greater. Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock

source. The minimum CLKR/X cycle times are based on internal logic speed; the maximum usable speed may be lower due to EDMA

limitations and AC timing requirements.

(4)

This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the reasonable range of 40/60 duty cycle.

DM643 Peripheral Information and Electrical Specifications

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