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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TMS320DM643 датащи(PDF) 30 Page - Texas Instruments |
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TMS320DM643 датащи(HTML) 30 Page - Texas Instruments |
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30 / 160 page  www.ti.com TMS320DM643 Video/Imaging Fixed-Point Digital Signal Processor SPRS269A – FEBRUARY 2005 – REVISED APRIL 2005 Table 2-4. Terminal Functions (continued) SIGNAL IPD/ TYPE(1) DESCRIPTION IPU(2) NAME NO. HD31/MRCLK(3) G1 HD30/MCRS(3) H3 HD29/MRXER(3) G2 HD28/MRXDV(3) J4 HD27/MRXD3(3) H2 HD26/MRXD2(3) J3 HD25/MRXD1(3) J1 HD24/MRXD0(3) K4 HD23 K1 HD22/MTCLK(3) L4 Host-port data (I/O/Z) [default] or EMAC transmit/receive or control pins HD21/MCOL(3) K2 As HPI data bus HD20/MTXEN(3) L3 • Used for transfer of data, address, and control HD19/MTXD3(3) L2 • Host-Port bus width user-configurable at device reset via a 10-k Ω resistor pullup/pulldown resistor on the HD5 pin: HD18/MTXD2(3) M4 Boot Configuration: HD17/MTXD1(3) M2 • HD5 pin = 0: HPI operates as an HPI16. HD16/MTXD0(3) M3 I/O/Z (HPI bus is 16 bits wide. HD[15:0] pins are used and the remaining HD15 T3 HD[31:16] pins are reserved pins in the high-impedance state.) HD14 U1 • HD5 pin = 1: HPI operates as an HPI32. (HPI bus is 32 bits wide. All HD[31:0] pins are used for host-port operations.) HD13 U3 HD12 U2 For superset devices like DM643, the HD31 through HD16 pins can also function as EMAC transmit/receive or control pins (when MAC_EN pin = 1). For more HD11 U4 details on the EMAC pin functions, see the Ethernet MAC (EMAC) peripheral HD10 V1 section of this table and for more details on how to configure the EMAC pin functions, see the device configuration section of this data sheet. HD9 V3 HD8 V2 HD7 W2 HD6 W4 HD5 Y1 HD4 W3 HD3 Y2 HD2 Y4 HD1 AA1 HD0 Y3 EMIFA (64-bit) – CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY ACE3 L26 O/Z IPU EMIFA memory space enables ACE2 K23 O/Z IPU • Enabled by bits 28 through 31 of the word address ACE1 K24 O/Z IPU • Only one pin is asserted during any external data access ACE0 K25 O/Z IPU ABE7 T22 O/Z IPU ABE6 T23 O/Z IPU EMIFA byte-enable control ABE5 R25 O/Z IPU • Decoded from the low-order address bits. The number of address bits or ABE4 R26 O/Z IPU byte enables used depends on the width of external memory. ABE3 M25 O/Z IPU • Byte-write enables for most types of memory ABE2 M26 O/Z IPU • Can be directly connected to SDRAM read and write mask signal (SDQM) ABE1 L23 O/Z IPU ABE0 L24 O/Z IPU 30 Device Overview |
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