TMS320DM643 datasheet(31/160 Pages) TI

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TMS320DM643

Video/Imaging Fixed-Point Digital Signal Processor

SPRS269A – FEBRUARY 2005 – REVISED APRIL 2005

Table 2-4. Terminal Functions (continued)

SIGNAL

IPD/

TYPE(1)

DESCRIPTION

IPU(2)

NAME

NO.

EMIFA peripheral data transfer, allows direct transfer between external periph-

APDT

M22

O/Z

IPU

erals

EMIFA (64-bit) – BUS ARBITRATION

AHOLDA

N22

IPU

EMIFA hold-request-acknowledge to the host

AHOLD

W24

IPU

EMIFA hold request from the host

ABUSREQ

P22

IPU

EMIFA bus request output

EMIFA (64-bit) – ASYNCHRONOUS/SYNCHRONOUS MEMORY CONTROL

EMIFA external input clock. The EMIFA input clock (AECLKIN, CPU/4 clock, or

CPU/6 clock) is selected at reset via the pullup/pulldown resistors on the

AECLKIN

H25

IPD

AEA[20:19] pins.

AECLKIN is the default for the EMIFA input clock.

EMIFA output clock 2. Programmable to be EMIFA input clock (AECLKIN,

AECLKOUT2

J23

O/Z

IPD

CPU/4 clock, or CPU/6 clock) frequency divided-by-1, -2, or -4.

EMIFA output clock 1 [at EMIFA input clock (AECLKIN, CPU/4 clock, or CPU/6

AECLKOUT1

J26

O/Z

IPD

clock) frequency].

EMIFA asynchronous memory read-enable/SDRAM column-address

strobe/programmable synchronous interface-address strobe or read-enable

AARE/

•

For programmable synchronous interface, the RENEN field in the CE Space

ASDCAS/

J25

O/Z

IPU

Secondary Control Register (CExSEC) selects between ASADS and ASRE:

ASADS/ASRE

If RENEN = 0, then the ASADS/ASRE signal functions as the ASADS signal.

If RENEN = 1, then the ASADS/ASRE signal functions as the ASRE signal.

AAOE/

EMIFA asynchronous memory output-enable/SDRAM row-address

ASDRAS/

J24

O/Z

IPU

strobe/programmable synchronous interface output-enable

ASOE

AAWE/

EMIFA asynchronous memory write-enable/SDRAM write-enable/programmable

ASDWE/

K26

O/Z

IPU

synchronous interface write-enable

ASWE

EMIFA SDRAM clock-enable (used for self-refresh mode).

ASDCKE

L25

O/Z

IPU

•

If SDRAM is not in system, ASDCKE can be used as a general-purpose

output.

EMIFA synchronous memory output-enable for ACE3 (for glueless FIFO

ASOE3

R22

O/Z

IPU

interface)

AARDY

L22

IPU

Asynchronous memory ready input

Device Overview

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