DSP56857 datasheet(162/662 Pages) FREESCALE

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CGM Functional Detail

5685X Digital Signal Controller User Manual, Rev. 4

6-12

Freescale Semiconductor

6.3.6.2 PLL Parametric Influences on Reaction Time

Lock time is designed to be as short as possible while still providing the highest possible stability.

Many factors directly and indirectly affect the lock time.

The most critical parameter affecting the reaction time of the PLL, is the Reference Frequency

(Fref). This frequency is the input to the phase detector and controls how often the PLL makes

corrections. For stability, the corrections must be small compared to the desired frequency, so

several corrections are required to reduce the frequency error. Therefore, the slower the

Reference Frequency (Fref), the longer it takes to make these corrections.

Temperature and processing also can affect acquisition time because the electrical characteristics

of the PLL change. The part operates as specified as long as these influences stay within the

specified limits.

6.4 CGM Functional Detail

The CGM controls the PLL, detects PLL lock, and is used to generate the master clock to the

SIM. The CPU clock is one half the frequency of the master clock while the IPBus clock is one

fourth the frequency. The SIM handles these clock divisions. The master clock source can be

either the oscillator output or the analog PLL output. The oscillator output (Fref) will typically be

4MHz, but a faster active clock can be driven into the XTAL pin at speeds of up to 240MHz. The

PLL output can be up to 240MHz.

In order to use the PLL, the proper divide by factor and post scaler values should be programmed

into the CGMDB register. Next, the PLL is turned on by setting the Power-Down (PDN) bit in

the CGMCR to zero. The user should then wait for the PLL to achieve lock before changing the

SEL bit to select the PLL output as the master clock.

6.4.1 PLL Frequency Lock Detector

This CGM function monitors the VCO output clock and sets the LCK1 and LCK0 bits in the

CGM Control register based on the frequency accuracy. The lock detector is enabled with the

LCKON bit of the CGMCR as well as the PDN bit. Once enabled, the detector starts two

counters whose outputs are periodically compared. The input clocks to these counters are the

VCO output clock divided by the divide-by factor, feedback, and the crystal reference clock,

Fref. The period of the pulses being compared cover one whole period of each clock because the

feedback clock doesn’t guarantee a 50 percent duty cycle.

Counts are compared after 16, 32, and 64 cycles. If the counts match after 32 cycles, the LCK0

bit is set to 1. If the counts match after 64 cycles, the LCK1 bit is also set. The LCK bits stay set

until the counts fail to match or if a new value is written to the PLLDB field or on reset caused by

LCKON, PDN, or chip level reset. When the circuit sets LCK1, the two counters are reset and

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