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DSP56857 датащи(PDF) 160 Page - Freescale Semiconductor, Inc |
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DSP56857 датащи(HTML) 160 Page - Freescale Semiconductor, Inc |
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160 / 662 page ![]() PLL (Phase Locked Loop) Circuit Detail 5685X Digital Signal Controller User Manual, Rev. 4 6-10 Freescale Semiconductor where m is the value on the postscaler and can range from 0 to 7. Example: Let Fref = 32MHz, n = 4, and m = 3, using the formulas gives: Fpll_out = (32MHz × (4+1)) / 8 Fpll_out = 20MHz. For the 4MHz input crystal the valid range of n will be from 19 to 59, producing the same VCO output range, 80MHz to 240MHz. 6.3.6 PLL Lock Time User Notes The PLL’s Voltage Controlled Oscillator (VCO) has a characterized operating range extending from 80MHz to 240MHz. The PLL is programmable via a divide by n+1 register, able to take on values varying between 1 and 128. For higher values of n, PLL lock time becomes an issue. It is recommended to avoid values of n resulting in the VCO frequency being greater than 240MHz. The graphic in Figure 6-7 depicts the range of recommended output frequencies of VCO_OUT, plotting n versus the input frequency (Fref). The lower the value of n, the quicker the PLL will be able to lock. |
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