DSP56857 datasheet(159/662 Pages) FREESCALE

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PLL (Phase Locked Loop) Circuit Detail

On-Chip Clock Synthesis (OCCS), Rev. 4

Freescale Semiconductor

6-9

6.3.1 Phase Frequency Detector

The Phase Frequency Detector (PFD) compares the clock signal from the feedback divider to the

input clock. When the input clock comes before the feedback clock the PFD generates a down

pulse signal. The down pulse signal continues until the feedback clock signal arrives. If the

feedback clock arrives at the PFD before the input clock, the PFD generates an up pulse,

continuing until the input clock signal arrives.

6.3.2 Charge Pump

The Charge Pump draws charge into or out of the Loop Filter depending upon the signals from

the Phase Frequency Detector. As charge is added to the Loop Filter the VCO control voltage

increases. As charge is pulled out of the Loop Filter, the VCO control voltage decreases.

6.3.3 Loop Filter

The Loop Filter produces a voltage proportional to the amount of charge pumped into or out of

the Loop Filter by the charge pump. The Loop Filter is a single pole RC filter.

6.3.4 Voltage Controlled Oscillator

The Voltage Controlled Oscillator (VCO) produces a frequency inversely proportional to the

value of the control voltage signal coming out of the Loop Filter. The VCO gain is approximately

109MHz/Volt. The VCO has a frequency range of 80MHz to 380MHz with a center frequency of

240MHz.

6.3.5 Down Counter

The Down Counter is a programmable divide by n counter where the divide integer n is user-set

to develop the PLL output frequency of interest. By presenting only one return pulse out of n

input pulses to the return clock of the phase frequency detector, the PFD will drive the charge

pump to raise the VCO frequency until the Down Counter return signal is in frequency and phase

lock with the input clock signal. The output of the VCO will, therefore, be n times the frequency

of the input clock signal. The value of n has a valid range of 19 to 119. The selected value of n

depends upon the desired VCO output frequency and the input clock frequency (Fref). For the

2MHz input crystal the valid range of n will range from 39 to 119, producing a VCO frequency

output of 80MHz to 240MHz according to the formula:

Fvco_out = Fref

× (n+1)

The VCO’s output frequency is routed through a postscaler so the final PLL output frequency is

given by:

Fpll_out = Fvco_out / 2

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