DSP56857 datasheet(54/662 Pages) FREESCALE

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56800E Core Description

5685X Digital Signal Controller User Manual, Rev. 4

1-22

Freescale Semiconductor

1.4.12.3 PLL

The PLL in the 56800E core provides the following features:

•

The PLL generates output frequencies up to 240MHz from a 2 - 4MHz input

•

The PLL can be bypassed to use oscillator or prescalar outputs directly

1.4.12.4 Clock Generation Module

This contains registers used to control clock generation and select clock sources:

•

There is a choice of time of day clock prescalers

•

The PLL frequency postscaler and enable control

•

Selection of master clock source to be PLL ,or OSC and glitch-free clock switching

•

PLL postscaler supports PLL output division by 1, 2, 4, 8, 16, 64,or 128

1.4.12.5 Time of Day Clock Options

These options provide:

•

A choice of two TOD clock prescalers

•

Low power/128 prescaler in OSC module for input clock frequencies to 4MHz

•

High frequency two stage/1-4096 and /2 prescaler in CGM module for input clock

frequencies to 240MHz OSC TOD prescaler

1.4.13 Resets

The 5685x device reset circuitry provides these features:

•

Integrated POR release occurs when VDD exceeds 1.35V and VDDA exceeds 2.45V

•

Reset pin

•

Software reset

•COP reset

1.4.14 IPBus Bridge

The IPBus architecture supports a variety of on-chip peripherals, including:

•

External Memory Interface (EMI) module

•

Serial Communication Interface (SCI) module

•

16-bit Timer (TMR) module

•

Computer Operating Properly (COP) module

•

Time of Day (TOD) module

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