DSP56857 datasheet(161/662 Pages) FREESCALE

161 / 662 page

PLL (Phase Locked Loop) Circuit Detail

On-Chip Clock Synthesis (OCCS), Rev. 4

Freescale Semiconductor

6-11

Figure 6-7. PLL Output Frequency vs. Input Frequency

The lock time of the PLL is, in many applications, the most critical PLL design parameter. Proper

use of the PLL ensures the highest stability and lowest lock time.

6.3.6.1 PLL Lock Time Determination

Typical control systems refer to the lock time as the reaction time, within specified tolerances, of

the system to a step input. In a PLL the step input occurs when the PLL is turned on or when it

suffers a noise hit. The tolerance is usually specified as a percent of the step input or when the

output settles to the desired value plus or minus a percent of the frequency change. Therefore, the

reaction time is constant in this definition regardless of the size of the step input.

When the PLL is coming from a powered down state (PDN is high) to a powered up condition

(PDN is low) the maximum lock time is 10msec.

Other systems refer to lock time as the time the system takes to reduce the error between the

actual output and the desired output to within specified tolerances. Therefore, the lock time varies

according to the original error in the output. Minor errors may be shorter or longer in many cases.

100

1000

Fref [MHz]

Fvco_out = 80

Fvco_out = 240

The recommended VCO output range is bounded by

a high frequency of 240 MHz and a low frequency of

80 MHz. The lower the value of CGMDB[PLLDB]

("n"), the faster the lock time for the PLL.

DSP56857 датащи(PDF) 161 Page - Freescale Semiconductor, Inc