DSP56857 datasheet(158/662 Pages) FREESCALE

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PLL (Phase Locked Loop) Circuit Detail

5685X Digital Signal Controller User Manual, Rev. 4

6-8

Freescale Semiconductor

enabled, but that is enough to keep TIME_CLK and the associated COP counter alive and

running. Fref is held quiescent.

When waking up from this deep stop, the PLL will need to be re-started, lock status

re-queried and the PLL output re-selected to source MSTR_CLK.

2. Case where CGMCR[TOD_SEL] =1

A STOP instruction will result in the MSTR_CLK clock source being forced back to Fref

and the PLL being powered down (PLL_SHUTDOWN asserts). If CGMCR[TOD_SEL]

is 1 when the STOP instruction is executed, then the SIM will not assert OSC_LOWPWR

for in doing so, the TIME_CLK (and COP) would be killed. This is usually an undesirable

situation from an applications perspective.

3. Fast STOP Recovery

A Fast STOP Recovery is available in which neither the OSC_LOWPWR or

PLL_SHUTDOWN signal are asserted. As such, no time is required to re-start the PLL,

but it comes at the cost of increased power consumption by the PLL during STOP. Fast

Stop Recovery is available by setting the OMR register’s bit 6 to 1.

For further details on STOP and Fast STOP Recovery, please see Section 4.9, Power Mode

Controls.

6.3 PLL (Phase Locked Loop) Circuit Detail

Figure 6-6. PLL Block Diagram

Phase/Freq

Fref

Detector

DOWN

VCO_OUT

VCO

PLL_OUT

Postscaler

Down Counter

(n = 19 to 119)

Charge

Loop

Pump

Filter

Lock Detector

(part of CGM)

Loss of Lock Interrupt

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