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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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DSP56857 датащи(PDF) 46 Page - Freescale Semiconductor, Inc |
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DSP56857 датащи(HTML) 46 Page - Freescale Semiconductor, Inc |
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46 / 662 page  56800E Core Description 5685X Digital Signal Controller User Manual, Rev. 4 1-14 Freescale Semiconductor • Full-precision integer multiplication • 32-bit logical and shifting operations • Second read in dual read instruction can access off-chip memory • Loop Count (LC) register extended to 16 bits • Support for nested DO looping through additional loop address and count registers • Loop address and hardware stack extended to 24 bits • Three additional interrupt levels with a software interrupt for each level • Enhanced On-Chip Emulation (EOnCE) with three debugging modes: — non-intrusive real-time debugging — minimally intrusive real-time debugging — break point and step modes (core is halted) 1.4.3 System Architecture and Peripheral Interface The 56800E system architecture encompasses all the on-chip components, including the core, on-chip memory, peripherals, and buses necessary to connect them. Figure 1-6 shows the overall system architecture for a device with an external bus. Figure 1-6. 56800E Chip Architecture with External Bus External Data External Address IPBus PDB PAB XAB1 CDBR CDBW XAB2 XDB2 Peripheral Peripheral Peripheral 56800E Core IPBus Interface External Bus Interface Data Memory Program Memory |
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