DSP56857 datasheet(88/662 Pages) FREESCALE

88 / 662 page

Power, Ground and Peripheral Signals

5685X Digital Signal Controller User Manual, Rev. 4

2-20

Freescale Semiconductor

Table 2-14. Clock and Phase Lock Loop Signals

Signal Name

Signal Type

Signal Description

853

Pins

854

Pins

855

Pins

857

Pins

858

Pins

EXTAL

Input

External Crystal Oscillator Input—This input

should be connected to an external crystal. If an

external clock source other than a crystal oscillator

is used, EXTAL must be tied off.

CLKO

Output

Clock Output—This pin outputs a buffered clock

signal. When enabled, this signal is the system

clock divided by four.

XTAL

Input / Output

Crystal Oscillator Output—This output connects

the internal crystal oscillator output to an external

crystal. If an external clock source other than a

crystal oscillator is used, XTAL must be used as

the input and the EXTAL connected to VDDA /2.

Table 2-15. JTAG/EOnCE Signals

Signal Name

Signal Type

Signal Description

853

Pins

854

Pins

855

Pins

857

Pins

858

Pins

TCK

Input

Test Clock Input—This input pin provides a gated

clock to synchronize the test logic and to shift

serial data to the JTAG/EOnCE port. The pin is

connected internally to a pull-down resistor.

TDI

Input

Test Data Input—This input pin provides a serial

input data stream to the JTAG/EOnCE port. It is

sampled on the rising edge of TCK and has an

on-chip pull-up resistor.

TDO

Output(Z)

Test Data Output—This tri-statable output pin

provides a serial output data stream from the

JTAG/EOnCE port. It is driven in the Shift-IR and

Shift-DR controller states, and changes on the

falling edge of TCK.

TMS

Input

Test Mode Select Input—This input pin is used to

sequence the JTAG TAP controller’s state

machine. It is sampled on the rising edge of TCK

and has an on-chip pull-up resistor.

TRST

Input

Test Reset—As an input, a low signal on this pin

provides a reset signal to the JTAG TAP controller.

To ensure complete hardware reset, TRST should

be asserted whenever RESET is asserted. The

only exception occurs in a debugging environment

when a hardware reset is required and it is

necessary not to rest the JTAG/EOnCE module. In

this case, assert RESET. Do not assert TRST.

Input / Output

Debug Enable—This is an open-drain,

bidirectional, active low signal. As an input, it is a

means of entering debug mode of operation from

an external command controller. As an output, it is

a means of acknowledging the chip has entered

debug mode.

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