DSP56857 datasheet(17/662 Pages) FREESCALE

17 / 662 page

LIST OF FIGURES

List of Figures, Rev. 4

Freescale Semiconductor

1-1

56853 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7

1-2

56854 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8

1-3

56855 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9

1-4

56857 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10

1-5

56858 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11

1-6

56800E Chip Architecture with External Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14

1-7

56800E Core Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16

1-8

IPBus Bridge Interface With Other Main Components

System Side Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-24

1-9

2-1

56853 Signals Identified by Functional Group2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5

2-2

56854 Signals Identified by Functional Group2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

2-3

56855 Signals Identified by Functional Group2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

2-4

56857 Signals Identified by Functional Group2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8

2-5

56858 Signals Identified by Functional Group2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9

3-1

56853 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6

3-2

56854 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7

3-3

56855 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7

3-4

56857 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8

3-5

56858 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8

4-1

System Integration Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5

4-2

SIM Register Map Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8

5-1

EMI Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5

5-2

EMI Register Map Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7

5-6

Data Bus Contention Timing Requiring MDAR Field Assertion . . . . . . . . . . . . . . 5-12

5-8

External Read Cycle with Clock and RWS = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14

5-9

External Read Cycle with RWS = 1, RWSH = 0 and RWSS = 0 . . . . . . . . . . . . . 5-15

5-10

External Read Cycle with RWSS = RWS = 1, and RWSH = 0 . . . . . . . . . . . . . . . 5-16

5-11

External Read Cycle RWS = RWSH = 1 and RWSS = 0 . . . . . . . . . . . . . . . . . . . 5-17

5-12

External Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18

5-13

External Write Cycle with WWS = 1, WWSH = 0, and WWSS = 0 . . . . . . . . . . . . 5-19

5-14

External Write Cycle with WWSS = 1, WWS = 0 and WWSH = 0 . . . . . . . . . . . . 5-20

5-15

External Write Cycle with WWS = 0, WWSH = 1, WWSS = 0 . . . . . . . . . . . . . . . 5-21

5-16

External Write Cycle with WWSS = WWS = 1 and WWSH = 0 . . . . . . . . . . . . . . 5-22

5-17

External Write Cycle with WWS = WWSH = 1 (WWSS = 0) . . . . . . . . . . . . . . . . . 5-23

6-1

OCCS Integration Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3

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