DSP56857 datasheet(166/662 Pages) FREESCALE

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OCCS Resets

5685X Digital Signal Controller User Manual, Rev. 4

6-16

Freescale Semiconductor

•

010 = PLL output is divided by four

•

011 = PLL output is divided by eight

•

100 = PLL output is divided by 16

•

101 = PLL output is divided by 32

•

110 = PLL output is divided by 64

•

111 = PLL output is divided by 128

6.6.2.2 Reserved—Bits 12–7

This bit field is reserved or not implemented. It is read as 0, but cannot be modified by writing.

6.6.2.3 PLL Divide-By (PLLDB)—Bits 6–0

The VCO output frequency is controlled by the PLL divide-by value. Each time a new value is

written into the PLLDB field, the Lock Detector circuit is reset. Before changing the divide-by

value, it is recommended the SEL bit be set to choose the oscillator output. The VCO output

frequency is determined by using the following formula:

Fvco_out = Fref

× (PLLDB + 1)

6.6.3 Clock Generation Module (CGM) Time-of-Day Register

Figure 6-11. CGM Time-of-Day Register (CGMTOD)

See Programmer’s Sheet on Appendix page B-17

6.6.3.1 Reserved—Bits 15–12

This bit field is reserved or not implemented. It is read as 0, but cannot be modified by writing.

6.6.3.2 TOD Scale Factor (TOD)—Bits 11–0

The output of the oscillator is divided by (TOD + 1) and then divided by 2, generating the

TIME_CLK used by the COP module when TOD_SEL is high. The value of TOD should be

chosen to result in a TOD clock frequency in the range of 15.12KHz to 31.25KHz. This register

is only reset during Power-On Reset (POR).

6.7 OCCS Resets

The CGM registers are reset by a chip level reset. This forces all registers to their reset state and

selects the oscillator output as the master clock source for the SIM.

Base + $2

Read

TOD

Write

Reset

000

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