DSP56857 datasheet(30/662 Pages) FREESCALE

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5685X Digital Signal Controller User Manual, Rev. 4

xxviii

Freescale Semiconductor

Manual Conventions

Conventions used in this manual:

•

Bits within registers are always listed from Most Significant Bit (MSB) to Least Significant

Bit (LSB).

•

Bits within a register are formatted AA[n:0] when more than one bit is involved in a

description. For purposes of description, the bits are presented as if they are contiguous

within a register. However, this is not always the case. Refer to the programming model

diagrams or to the programmer’s sheets to see the exact location of bits within a register.

•

When a bit is described as set, its value is set to one. When a bit is described as cleared, its

value is set to zero.

•

Pins or signals asserted low, made active when pulled to ground, have an over-bar above

their name. For example, the SS0 pin is asserted low.

•

Hex values are indicated with a dollar sign ($) preceding the hex value, as follows: $FFFB

is the X memory address for the Interrupt Priority Register (IPR).

•

Code examples follow in a single spaced font.

•

Pins or signals listed in code examples asserted as low have a tilde in front of their names.

In the previous example, line three refers to the SS0 pin, shown as ~SS0.

•

The word reset is used in three different contexts in this manual. The word pin is a generic

term for any pin on the chip. They are described as:

— a reset pin is always written as RESET, in uppercase, using the over bar

— the processor state occurs when the RESET pin is asserted. It is always written as Reset,

with a capitalized first letter

— the word reset refers to the reset function. It is written in lowercase, without italics, used

here only for differentiation. The word may require a capital letter as style dictates, such

as in headings and captions

•

The word assert means a high true (active high) signal is pulled high to VDD, or a low true

(active low) signal is pulled low to ground. The word deassert means a high true signal is

pulled low to ground, or a low true signal is pulled high to VDD.

BFSET

#$0007,X:PCC ; Configure:

line 1

; MISO0, MOSI0, SCK0 for SPI master

line 2

; ~SS0 as PC3 for GPIO

line 3

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