DSP56857 datasheet(164/662 Pages) FREESCALE

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5685X Digital Signal Controller User Manual, Rev. 4

6-14

Freescale Semiconductor

6.6.1.2 Lock 1 Status (LCK1)—Bit 13

This bit shows the status of the lock detector state for the LCK1 circuit. Changes in the state of

this bit can be used to cause interrupts in conjunction with the LCK1 Interrupt Enable bits. The

LCK1 interrupt is cleared by writing 1 to this bit.

•

0 = PLL not locked

•

1 = PLL locked

6.6.1.3 Lock 0 Status (LCK0)—Bit 12

This bit shows the status of the lock detector state for the LCK0 circuit. Changes in the state of

this bit can be used to cause interrupts in conjunction with the LCK0 Interrupt Enable bits. The

LCK0 interrupt is cleared by writing 1 to this bit.

•

0 = PLL not locked

•

1 = PLL locked

6.6.1.4 Clock Source Select (SEL)—Bit 11

This bit is used to control the source of the master clock to the SIM.

•

0 = Oscillator output selected by default

•

1 = PLL output selected

6.6.1.5 Reserved—Bits 10–7

This bit field is reserved or not implemented. It is read as 0, but cannot be modified by writing.

6.6.1.6 Lock 1 Interrupt Enable (LCK1_IE)—Bits 6–5

An optional interrupt can be generated if the PLL lock status bit (LCK1) changes.

•

00 = Disable interrupt by default

•

01 = Enable interrupt on rising edge of LCK1

•

10 = Enable interrupt on falling edge of LCK1

•

11 = Enable interrupt on any edge of LCK1

6.6.1.7 Lock 0 Interrupt Enable (LCK0_IE)—Bits 4–3

An optional interrupt can be generated if the PLL Lock (LCK0) status bit changes.

•

00 = Disable interrupt by default

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