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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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DSP56857 датащи(PDF) 98 Page - Freescale Semiconductor, Inc |
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DSP56857 датащи(HTML) 98 Page - Freescale Semiconductor, Inc |
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98 / 662 page  Memory Maps 5685X Digital Signal Controller User Manual, Rev. 4 3-10 Freescale Semiconductor 3.3.1.2 Peripheral Mapped Registers The following tables provide lists of all of the Peripheral Memory mapped registers in the 5685x devices. Each is discussed in this manual. Reserved $8E OBCNTR EOnCE Breakpoint Unit [0] Counter Reserved Reserved Reserved $8A OESCR External Signal Control Register Reserved Table 3-2. System Integration Module Register Address Map (SYS_BASE = $1FFF08) see Chapter 4 Address Offset Register Acronym Register Name Access Type Chapter Location Base + $0 SCR SIM Control Register Read/Write Section 4.6.1 Base + $1 SCD1 Software Control Data 1 Register Read/Write Section 4.6.2 Base + $2 SCD2 Software Control Data 2 Register Read/Write Section 4.6.3 Table 3-3. External Memory Interface Registers Address Map (EMI_BASE = $1FFE40) see Chapter 5 Address Offset Register Acronym Register Name Access Type Chapter Location Base + $0 CS0 Chip Select Address & Block Size Read/Write Section 5.6.1 Base + $1 CS1 Chip Select Address & Block Size Read/ Write Base + $2 CS2 Chip Select Address & Block Size Read/Write Base + $3 CS3 Chip Select Address & Block Size Read/Write Base + $8 CSOR_0 Chip Select Options Register 0 Read/Write Section 5.6.2 Base + $9 CSOR_1 Chip Select Options Register 1 Read/ Write Base + $A CSOR_2 Chip Select Options Register 2 Read/Write Base + $B CSOR_3 Chip Select Options Register 3 Read/Write Base + $10 BCR Bus Control Register Read/Write Section 5.6.3 Table 3-1. EOnCE Memory Map (EOnCE_BASE = $FFFF00) (Continued) Address Offset Register Acronym Register Name |
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