DSP56857 datasheet(28/662 Pages) FREESCALE

28 / 662 page

5685X Digital Signal Controller User Manual, Rev. 4

xxvi

Freescale Semiconductor

•

Chapter 7, Power-On Reset (POR) and Computer Operating Properly

(COP)—function monitors the core power supply and analog power supply.

•

Chapter 8, Interrupt Controller (ITCN)—describes how the IPBus Interrupt Controller

accepts interrupt requests from IPBus-based peripherals and presents them to the 56800E

core.

•

Chapter 9, Direct Memory Access (DMA)—transfers data between points in the memory

map without intervention by the CPU. The DMA controller allows movements of data to

and from internal data memory, or internal peripherals to occur in the background of CPU

operation.

•

Chapter 10, Serial Communications Interface (SCI)—presents the Serial

Communications Interface, communicating with devices such as codecs, other DSCs,

microprocessors, and peripherals to provide the primary data input path.

•

Chapter 11, Serial Peripheral Interface (SPI)—describes the Serial Peripheral

Interface, which communicates with external devices, such as Liquid Crystal Displays

(LCDs) and Microcontroller Units (MCUs).

•

Chapter 12, Enhanced Synchronous Serial Interface (ESSI)—details the Enhanced

Synchronous Serial Interface. It communicates with devices such as industry-standard

codecs, other DSCs, microprocessors, and peripherals to implementing the Serial

Peripheral Interface (SPI).

•

Chapter 13, Quad Timer (TMR)—outlines the internal Quad Timer devices available,

including features and registers.

•

Chapter 14, Time-Of-Day (TOD)—discusses instruction of the sequence of counters to

track elapsed time and its ability to track time up to 179.5 years, or 65,535 days.

•

Chapter 15, General Purpose Input/Output (GPIO)—describes how peripheral pins are

multiplexed with GPIO functions.

•

Chapter 16, Host Interface Eight (HI8)—provides host processors with DSC design

accesses.

•

Chapter 17, JTAG Port—explains the Joint Test Action Group (JTAG) testing

methodology and its capabilities with Test Access Port (TAP) and Enhanced OnCE (fully

explained in the Reference Manual).

•

Appendix A, Glossary—provides definitions of terms, peripherals, acronyms and

•

Appendix B, Programmer’s Sheets—provides concise, one location of registers and their

reference tables intended to simplify programming of the 5685x.

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