DSP56857 datasheet(51/662 Pages) FREESCALE

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56800E Core Description

5685X Overview, Rev. 4

Freescale Semiconductor

1-19

1.4.8 Address Generation Unit (AGU)

The Address Generation Unit (AGU) performs all of the calculations of effective addresses for

data operands in memory. It contains two address ALUs, allowing up to two 24-bit addresses to

be generated every instruction cycle:

1. One for either the Primary Data Address Bus (XAB1), or the Program Address Bus (PAB)

2. One for the Secondary Data Address Bus (XAB2)

The address ALU can perform both linear and modulo address arithmetic. The AGU operates

independently of the other core units, minimizing address-calculation overhead.

The AGU can directly address 224 (16M) words on the XAB1 and XAB2 buses. It can access 221

(2M) words on the PAB. The XAB1 bus can address byte, word, and long data operands. The

PAB and XAB2 buses can only address words in memory.

The AGU consists of the following registers and functional units:

•

Seven, 24-bit address registers (R0–R5 and N)

•

Four, 24-bit shadow registers for address registers (for R0, R1, M, and M01

•

A 24-bit dedicated Stack Pointer (SP) register

•

Two offset registers (N and N3)

•

A 16-bit modifier register (M01)

•

A 24-bit adder unit

•

A 24-bit modulo arithmetic unit

Each of the address registers (R0–R5) can contain either data or an address. All of these registers

can provide an address for the XAB1 and PAB address buses; addresses on the XAB2 bus are

provided by the R3 register. The N offset register can be used either as a general-purpose address

second 16-bit offset register (N3) is used only for offset or update values. The modifier register

(M01) selects between linear and modulo address arithmetic.

1.4.9 Program Controller and Hardware Looping Unit

The Program Controller is responsible for instruction fetching and decoding, interrupt

processing, hardware interlocking, and hardware looping. Actual instruction execution takes

place in the other core units, such as in the data ALU, AGU, or bit-manipulation unit.

The Program Controller contains the following:

•

An instruction latch and decoder

•

The hardware looping control unit

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