DSP56857 datasheet(165/662 Pages) FREESCALE

165 / 662 page

On-Chip Clock Synthesis (OCCS), Rev. 4

Freescale Semiconductor

6-15

•

01 = Enable interrupt on rising edge of LCK0

•

10 = Enable interrupt on falling edge of LCK0

•

11 = Enable interrupt on any edge of LCK0

6.6.1.8 Lock Detector On (LCKON)—Bit 2

•

0 = Lock detector disabled by default

•

1= Lock detector enabled

6.6.1.9

Time-of-Day Clock Source Select (TOD_SEL)—Bit 1

This bit is used to select between two possible TIME_CLK sources. The oscillator can generate

the TIME_CLK only when the input clock on either the EXTAL or XTAL pins in 4MHz or less.

When driving high speed clocks into XTAL, the CGM must generate the TIME_CLK using the

CGMTOD register. This bit is only reset by Power-On Reset (POR) conditions.

•

0 = TIME_CLK is generated by oscillator as default

•

1 = TIME_CLK is generated by CGM

6.6.1.10 PLL Power-Down (PDN)—Bit 0

The PLL can be turned off by setting the PDN bit to one. There is a four IPBus clock delay from

changing the bit to signaling the PLL. When the PLL is powered down, the clock select logic

automatically switches to the oscillator output in order to prevent loss of clock to the core.

•

0 = PLL turned on

•

1 = PLL powered down by default

6.6.2 Clock Generation Module (CGM) Divide-By Register

Figure 6-10. CGM Divide-By Register (CGMDB)

See Programmer’s Sheet on Appendix page B-16

6.6.2.1 PLL Post Scaler (POST)—Bits 15–13

The output of the PLL is postscaler by 1 to 128 based on this field. When changing this field, it is

recommended the SEL bit is set to choose the oscillator output, changing this field, then the SEL

bit is returned to selecting the PLL’s postscaler output.

•

000 = PLL output is divided by one by default

•

001 = PLL output is divided by two

Base + $1

Read

POST

PLLDB

Write

Reset

000

011

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