DSP56857 datasheet(116/662 Pages) FREESCALE

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Module Memory Map

5685X Digital Signal Controller User Manual, Rev. 4

4-8

Freescale Semiconductor

4.5 Module Memory Map

The System Integration Module (SIM) contains three programmable 16-bit registers. The address

range from $1FFF08 to $1FFF0F is allocated to the SIM. The register is accessed by each of the

eight-memory mapped addresses, delineated in Tables 4-7. To avoid unpredictable behavior,

reserved registers must not be written. A read from an address without an associated register

returns unknown data.

Input

CLK_SYS_CONT Input from DE input pad used to enter OnCE debug mode

OMR6_SD

Input

CLK_SYS_CONT From core OMR6 register to enable fast stop mode recovery

BSCAN_EBL

Input

—

From external TAP controller indicating boundary scan mode

Table 4-6. Derived Clock Inputs

Name

Type

Clock Domain

Function

CLK_SYS_CONT_IN

Input

CLK_SYS_CONT

Continuous clock fed by synthesized clock tree originating

at SIM output CLK_SYS_CONT

Table 4-7. System Integration Module Memory Map (SIM_BASE = $1FFF08)

Address Offset

Acronym

Access Type Chapter Location

Base + $0

SCR

SIM Control Register

Read/Write

Section 4.6.1

Base + $1

SCD1

Software Control Register 1

Read/Write

Section 4.6.2

Base + $2

SCD2

Software Control Register 2

Read/Write

Section 4.6.3

Add.

Offset

987654

321

SCR

BOOT MODE

CHIP REV

EOnCE

EBL

CLKOUT

DBL

PRAM

DBL

DRAM

DBL

STOP

DBL

WAIT

DBL

SCID1

SOFTWARE CONTROL DATA 1

SCD2

SOFTWARE CONTROL DATA 2

Read as 0

Reserved

Figure 4-2. SIM Register Map Summary

Table 4-5. Power Mode Control Inputs/Outputs (Continued)

Name

Type

Clock Domain

Function

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