DSP56857 datasheet(120/662 Pages) FREESCALE

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5685X Digital Signal Controller User Manual, Rev. 4

4-12

Freescale Semiconductor

4.6.1.4 Reserved—Bit 7

This bit is reserved or not implemented. It is a read/write bit, initializing to one.

4.6.1.5 Enhanced OnCE Enable (EOnCE_EBL)—Bit 6

The clock for the 56800E core On-Chip Emulator debug features is normally enabled with the

core TAP interface. Setting this bit continuously enables the clock. This powers the core to

perform I/O with its mapped EOnCE registers without regard for the TAP state. This is useful

when doing real time debugging.

•

0 = EOnCE clock to core is enabled only when core TAP is enabled

•

1 = EOnCE clock to core is always enabled

4.6.1.6 CLKOUT Disable (CLKOUT_DBL)—Bit 5

•

0 = CLKOUT (CLKO) output pin presents CLK_MSTR/8 (this is half the peripheral bus

clock frequency)

•

1 = CLKOUT (CLKO) output pin presents static zero

4.6.1.7 Program RAM Disable (PRAM_DBL)—Bit 4

•

0 = Internal program RAM enabled

•

1 = Internal program RAM disabled and accesses redirected to external memory

4.6.1.8 Data RAM Disable (DRAM_DBL)—Bit 3

Note:

This field replaces the EX bit in the core OMR.

•

0 = Internal data RAM enabled

•

1 = Internal data RAM disabled and accesses redirected to external memory

4.6.1.9 Software Reset (SW_RESET)—Bit 2

Writing 1 to this field results in the part to reset.

4.6.1.10 Stop Disable (STOP_DBL)—Bit 1

•

0 = The Stop mode is entered when the core executes a Stop instruction

•

1 = The core Stop instruction will not cause entry into the Stop mode

4.6.1.11 Wait Disable (WAIT_DBL)—Bit 0

•

0 = The Wait mode is entered when the core executes a Wait instruction

•

1 = The core Wait instruction will not cause entry into the Wait mode

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