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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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DSP56857 датащи(PDF) 113 Page - Freescale Semiconductor, Inc |
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DSP56857 датащи(HTML) 113 Page - Freescale Semiconductor, Inc |
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113 / 662 page  Block Diagram System Integration Module (SIM), Rev. 4 Freescale Semiconductor 4-5 Figure 4-1. System Integration Module Power Modes: Run, Wait, Pre-Stop, Stop *Cont SYS_CLK_IN is a synthesized clock tree fed by the CLK_SYS Cont output of SIM Power Mode Control P/D RAM Disable Software Control Reg 1 Software Control Reg 2 SIM Control Register Bus Interface IPBus Modes A, B, C Stop/Wait Disable IPBus Slow Write Clock Generator Master CLK Scan CLK IPBB Hold Off DRAM Hold Off Core Stall CLKOUT Disable NCLK Enable Pipelined Sys Clks Other Sys Clks 56800E Clks Periph Bus Clk Periph Bus Phase Hold Off Cont Sys Clk* Internal Clk POR Disable Reset SW Reset Pin Reset POR Reset COP Bscan Enable Reset Generator Reset POR Reset Reset Core Reset Reset TOD Cont Sys Clk In Cont Sys Clk In OSC_LOPWR PLL Shutdown P5STOP P5WAIT Int Pending JTDEBREQ/DE OMR6_SD |
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