DSP56857 datasheet(119/662 Pages) FREESCALE

119 / 662 page

System Integration Module (SIM), Rev. 4

Freescale Semiconductor

4-11

4.6.1.2.4 Boot Mode 3: Development Expanded Mode

The PRAM DISABLE is set to one, leaving internal data RAM enabled, but the internal program

RAM is disabled. All references to internal program memory space are subsequently directed to

external program memory. No code is loaded. The bootstrap program simply vectors to program

memory location P:$000000 using CS0 as the chip select.

4.6.1.2.5 Boot Mode 4: Bootstrap From Host Port–Single Strobe Clocking

The PRAM DISABLE remains at zero, leaving both internal program and data RAM enabled.

The bootstrap program configures the Host Port for single strobe access, loading program

memory from the Host Port before jumping to the start of the user code.

Note:

This mode becomes a reserved mode on parts lacking a host port interface.

4.6.1.2.6 Boot Mode 5: Bootstrap From Host Port–Dual Strobe Clocking

The PRAM DISABLE remains at zero, leaving both internal program and data RAM enabled.

The bootstrap program configures the Host Port for dual strobe access, loading program memory

from the Host Port before jumping to the start of the user code.

Note:

This mode becomes a reserved mode on parts lacking a host port interface.

4.6.1.2.7 Boot Mode 6: Bootstrap From SCI

The PRAM DISABLE remains at zero, leaving both internal program and data RAM enabled. It

configures the SCI for 38400 baud transfers with a 4MHz or 19200 with a 2MHz crystal. It also

enables the PLL to operate during the boot process. The bootstrap program then loads program

memory from the SCI port and jumps to the start of the user code. External clocking must be at

2MHz or 4MHz. It uses the PLL but leaves it off when complete. The data format is:

•

One start bit

•

Eight-data bits

•

No parity bit

•

One Stop bit

•

Flow Control off

4.6.1.2.8 Boot Mode 7: Reserved for Future Use

4.6.1.3 Chip Revision (CHIP REV)—Bits 11–8

Static read only value (currently 0001) indicating chip revision. This is intended to be used by

applications software to facilitate support of backwards compatibility. Changes to the

programming interface can be tied to their associated chip revision.

DSP56857 датащи(PDF) 119 Page - Freescale Semiconductor, Inc