DSP56857 datasheet(115/662 Pages) FREESCALE

115 / 662 page

Signal Description

System Integration Module (SIM), Rev. 4

Freescale Semiconductor

4-7

N1CLKEN

Input

CLK_MSTR

NCLK enable signal from 56800E Core

JHAWKCORETAP_EN

Input

CLK_MSTR

Re synchronized to CLK_SYS_CONT and used to disable

CLK_CPU_PCLK after reset if core tap disabled

CORE_STALL

Input

—

Core stall request from SBC for DMA mastership

Table 4-3. Reset Generator Inputs/Outputs

Name

Type

Clock Domain

Function

RST_CORE

Output

CLK_SYS_CONT Synchronized and extended reset to 56800E Core

RST_PERIPH

Output

CLK_SYS_CONT Synchronized and extended reset to general peripheral logic

RST_TOD

Output

CLK_SYS_CONT

Synchronized and extended reset to modules using only power

on reset (the TOD and COP modules)

RST_CGM

Output

CLK_OSC

Synchronized and extended reset to CGM module

RST_PIN

Input

—

Reset request from external reset pin

RST_POR

Input

—

Reset request from power-on reset module

RST_COP

Input

—

Reset request from COP module

Table 4-4. Register Inputs/Outputs

Name

Type

Clock Domain

Function

MODE_CBA

Input

—

From MODEC, B, A input pads, captured at reset in SIM control

PRAM_DBL

Output

CLK_IPB

Redirect program RAM accesses to external memory IF

DRAM_DBL

Output

CLK_IPB

Redirect data RAM accesses to external memory IF

STOP_DBL

Output

CLK_IPB

Direct the core to disable the STOP instruction

WAIT_DBL

Output

CLK_IPB

Direct the core to disable the WAIT instruction

Table 4-5. Power Mode Control Inputs/Outputs

Name

Type

Clock Domain

Function

STOPMD

Output

CLK_SYS_CONT Indicates SIM is in Stop mode

WAITMD

Output

CLK_SYS_CONT Indicates SIM is in Wait mode

RUNMD

Output

CLK_SYS_CONT Indicates SIM is in Run mode

OSC_LOPWR

Output

CLK_SYS_CONT

Puts oscillator into low power mode configuration during Stop

mode

PLL_SHUTDOWN

Output

CLK_SYS_CONT

Shuts down PLL and puts it into bypass mode when entering

Stop mode

P5STOP

Input

CLK_SYS_CONT Input from Core indicating Stop instruction executed

P5WAIT

Input

CLK_SYS_CONT Input from Core indicating Wait instruction executed

INT_PEND

Input

CLK_SYS_CONT Input from INTC indicating interrupt is pending

JTDEBREQ

Input

CLK_SYS_CONT Input from Core indicating a JTAG debug mode request

Table 4-2. Clock Generator Inputs/Outputs (Continued)

Name

Type

Clock Domain

Function

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