DSP56857 datasheet(117/662 Pages) FREESCALE

117 / 662 page

System Integration Module (SIM), Rev. 4

Freescale Semiconductor

4-9

4.6 Register Descriptions (SYS_BASE = $1FFF08)

4.6.1 SIM Control Register (SCR)

Figure 4-3. SIM Control Register (SCR)

See Programmer’s Sheet on Appendix page B-8

4.6.1.1 Reserved—Bit 15

This bit is reserved or not implemented. It is read as 0, but it cannot be modified by writing.

4.6.1.2 Boot Mode—Bits 14–12

These boot mode bits replace the mode bits in the 56800E OMR.

This field is set to the value on the input pins, MODA, MODB, and MODC, when the last active

reset source—reset pin, power-on reset—deasserts. Synchronous reset (software or COP) do not

update Boot mode assuming applications software will set the desired field value prior to the

reset. The core always begins execution after reset from the base on the on-chip ROM. The

software in ROM will perform one of the several boot actions based on the value of Boot mode.

Note:

A COP reset via COP_RST does not alter these registers since a COP reset by

definition occurs unexpectedly during system operation, therefore possibly no longer

providing the required MODE inputs.

Note:

A software reset via RST_SW does not alter these registers, thereby allowing users to

reboot in a different mode without altering the hardware.

The 56800E core begins execution from the base of the on-chip ROM. The software in ROM will

perform one of several boot actions based on the value of BOOT MODE.

Some Boot modes, specifically those transferring code to internal PRAM for execution, require

header data to synchronize the peripheral, define the transfer start address in PRAM, and define

the number of words to load. The following four points describe the required format for boot

mode:

1. The four byte ASCII sequence BOOT (mode 1 only)

2. Two words (4 bytes) defining the number of program words to be loaded (modes 0, 1, 4, 5,

and 6 only)

Base + $0

Read

BOOT MODE

CHIP REV

EOnCE

EBL

CLKOUT

DBL

PRAM

DBL

DRAM

DBL

RST

STOP

DBL

WAIT

DBL

Write

Reset

000

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