DSP56857 datasheet(114/662 Pages) FREESCALE

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Signal Description

5685X Digital Signal Controller User Manual, Rev. 4

4-6

Freescale Semiconductor

4.4 Signal Description

A description of the System Integration Module (SIM) signals are shown in Tables 4-1 through

Tables 4-6.

4.4.1 SIM Interface Signals

Table 4-1. IPBus Signals

Name

Type

Clock Domain

Function

CLK_IPB

Input

—

Peripheral bus clock

RD_DATA_Z

Output

CLK_IPB

Read data (tri-stateable)

WR_DATA

Input

CLK_IPB

Write data

ADDR

Input

CLK_IPB

R/W address (two LSBs of IPBus Address)

RWB

Input

CLK_IPB

Write enable (active low)

MODULE_EN

Input

CLK_IPB

Module enable (active low)

Table 4-2. Clock Generator Inputs/Outputs

Name

Type

Clock Domain

Function

CLK_SYS_DRAM

Output

CLK_MSTR

System clock to data RAM with hold off support

CLK_SYS_IPBB

Output

CLK_MSTR

System clock to IPBus Bridge with hold off support

CLK_SYS_CPUCLK

Output

CLK_MSTR

System clock to 56800E Core with hold off support

CLK_CPU_PCLK

Output

CLK_MSTR

Feeds PCLK input on 56800E Core

CLK_CPU_NCLK

Output

CLK_MSTR

Feeds NCLK input on 56800E Core

CLK_CPU_WCLK

Output

CLK_MSTR

Feeds WRAP_CLK input on 56800E Core

CLK_SYS_GENRI

Output

CLK_MSTR

General purpose system clock with hold off support

CLK_SYS_GENRI_INV

Output

CLK_MSTR

General purpose system clock with hold off support-inverted

CLK_SYS_CONT

Output

CLK_MSTR

Continuous system clock (feeds back into SIM)

CLK_PER_CONT

Output

CLK_MSTR

Peripheral bus clock

CLK_PER_CONT_INV

Output

CLK_MSTR

Inverted peripheral bus clock

CLK_CLKOUT

Output

CLK_MSTR

Output to CLKOUT output pad

PCLK_PHASE

Output

CLK_MSTR

Indicates peripheral clock phase (1=address 0=data)

HOLD OFF

Output

CLK_MSTR

Indicates at least one hold off control is asserted,

used to abort peripheral bus transactions

C7WAITST

Output

CLK_MSTR

Indicates to core if it’s system clock is to be stalled for reasons

other than a core reset (e.g. a hold off or core_stall)

CLK_MSTR

Input

CLK_MSTR

Master input clock from CGM module

CLK_OSC

Input

—

Master clock direct from oscillator bypassing CGM module

CLK_SCAN

Input

—

Scan mode clock

HOLD_DRAM

Input

—

Hold off request from data RAM

HOLD_IPBB

Input

CLK_MSTR

Hold off request from IPBus bridge

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