LTC6952 datasheet(29/80 Pages) AD

29 / 80 page

LTC6952

6952f

For more information www.analog.com

Preliminary Technical Data

Advance Product Information Subject to Change

Rev PrA

OPERATION

Figure 15. Flowchart to Determine the Best Synchronization Protocol for a Given Application

Inputs:

TP = Total number of JESD device clock/SYSREF Pairs

LNP = Number of JESD Pairs requiring low noise (< 100fs) device clocks

TS = Total number of stand alone clock signals

LNS = Number of required low noise (< 100fs) stand alone clocks

T = 2TP + TS

START

JESD204B Application?

Inputs:

T = Total number of clock signals

LNS = Number of required low noise (< 100fs) clocks

T ≤ 11 ?

Use EZSync Standalone

T ≤ 11 ?

T ≤ 56

AND TP ≤ 25

AND LNS ≤ 11 – 2P – 2LNP

AND LNP ≤ 5 – P ?

Use EZSync Multi-Chip with

Request Passthrough

(1 Controller and P Followers)

T ≤ 56

AND LNS ≤ 11 – 2P ?

Use ParallelSync with LTC6953

Reference Distribution (P Parallel Parts)

T ≤ 55

AND TP ≤ 25 ?

T ≤ 121

AND LNS ≤ 11 – P ?

T ≤ 121

AND TP ≤ 55

AND LNS ≤ 11 – P – 2LNP

AND LNP ≤ (55 – TP)/9 ?

Use Standard EZSync Multi-Chip

(1 Controller and P Followers)

Use Standard ParallelSync

Multi-Chip (P Parallel Parts)

Yes

6952 FC

Yes

NOTE: Ceiling() function means

round up to the next highest integer

P =Ceiling Max

T – 11

TP – 5

(

)

P =Ceiling

T – 11

P =Ceiling Max

(

)

P =Ceiling Max

(

)

P =Ceiling

T – 11

P =Ceiling Max

!11

!5.5

4.5

⎛

⎝

⎜

⎞

⎠

⎟

⎡

⎣

⎢

⎤

⎦

⎥

P =Ceiling

T ≤ 55 ?

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