LTC6952 datasheet(17/80 Pages) AD

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LTC6952

6952f

For more information www.analog.com

Preliminary Technical Data

Advance Product Information Subject to Change

Rev PrA

OPERATION

The LTC6952 is a high-performance integer-N PLL and

multi-output clock generator that operates up to 4.5GHz.

Utilizing Analog Devices’ proprietary EZSync and Paral-

lelSync standards, users of the LTC6952 can synchronize

clocks across multiple outputs and multiple chips. Using

an external low-noise VCO, the device is able to achieve

superior integrated jitter performance by the combination

of its extremely low in-band phase noise and excellent

output noise floor. For JESD204B subclass 1 applications,

the LTC6952 also provides several convenient methods

to generate SYSREF pulses.

REFERENCE INPUT BUFFER

The PLL’s reference frequency is applied differentially on

pins REF+ and REF–. These high-impedance inputs are

self-biased and should be AC coupled with 1µF capacitors

(see Figure 1 for a simplified schematic). Alternatively, the

inputs may be used single-ended by applying the refer-

ence frequency at REF– and bypassing REF+ to GND with

a 1µF capacitor. If the single-ended signal is greater than

2.7VP-P, then use a 47pF capacitor for the GND bypass.

Additional options are available through serial port register

h02 to further refine the application. Bit FILTR controls

the reference input buffer’s low-pass filter, and should

be set for sine wave signals based upon fREF to limit the

reference’s wideband noise. The FILTR bit must be set

correctly to reach the LNORM normalized in-band phase

noise floor. See Table 1 for recommended settings. Square

wave inputs will have FILTR set to a “0”.

Table 1. FILTR Programming

FILTR

Sine Wave fREF

Square Wave fREF

< 20MHz

N/A

≥ 20MHz

All fREF

The BST bit should be set based upon the input signal level

to prevent the reference input buffer from saturating. The

BST programming is the same whether the input is a sine

wave or a square wave. See Table 2 for recommended

settings and the Applications Information section for

programming examples.

Table 2. BST Programming

BST

VREF

< 1.6 VP-P

≥ 1.6 VP-P

Reference Peak Detector

A reference input peak detection circuit is provided on the

REF± inputs to detect the presence of a reference signal

and provides the REFOK and REFOK status flags available

through both the STAT output and serial port register

h00. REFOK is the logical inverse of REFOK. The circuit

has hysteresis to prevent the REFOK flag from chattering

at the detection threshold. The reference peak detector

may be powered-down using the PDREFPK bit found in

The peak detector approximates an RMS detector, therefore

sine and square wave inputs will give different detection

thresholds by a factor of 4/π. See Table 3 for REFOK

detection values.

Table 3. REFOK, REFOK Status Output vs REF Input

REFOK

Sine Wave fREF

Square Wave fREF

≥ 350mVP–P

≥ 275mVP–P

< 100mVP–P

< 75mVP–P

2.1k

REF+

REF–

2.1k

400Ω

6952 F01

1.9V

BST

BIAS

VREF

FILTR

Figure 1. Simplified REF Interface Schematic

A high quality signal must be applied to the REF± inputs

as they provide the frequency reference to the entire PLL.

To achieve the part’s in-band phase noise performance,

apply a sine wave signal of at least 6dBm into 50Ω, or a

square wave of at least 0.5VP-P, with slew rate of at least

20V/µs. See the Applications Information section for more

information on reference input signal requirements and

interfacing.

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