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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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LTC6952 датащи(PDF) 1 Page - Analog Devices |
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LTC6952 датащи(HTML) 1 Page - Analog Devices |
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1 / 80 page  LTC6952 1 6952f For more information www.analog.com Preliminary Technical Data Advance Product Information Subject to Change Rev PrA TYPICAL APPLICATION FEATURES DESCRIPTION Ultralow Jitter, 4.5GHz PLL with 11 Outputs and JESD204B Support The LTC®6952 is a high performance, ultralow jitter, JESD204B clock generation and distribution IC. It includes a Phase Locked Loop (PLL) core, consisting of a reference divider, phase-frequency detector (PFD) with a phase-lock indicator, ultralow noise charge pump and integer feedback divider. The LTC6952’s eleven outputs can be configured as up to five JESD204B subclass 1 device clock/SYSREF pairs plus one general purpose output, or simply eleven general purpose clock outputs for non-JESD204B applica- tions. Each output has its own individually programmable frequency divider and output driver. All outputs can also be synchronized and set to precise phase alignment using individual coarse half-cycle digital delays and fine analog time delays. For applications requiring more than eleven total outputs, multiple LTC6952s can be connected together using the EZSync or ParallelSync synchronization protocols. APPLICATIONS n JESD204B, Subclass 1 SYSREF Signal Generation n Low Noise Integer-N PLL n Additive Output Jitter < 6fsRMS (Integration BW = 12kHz to 20MHz, f = 4.5GHz) n Additive Output Jitter 65fsRMS (ADC SNR Method) n EZSync™, ParallelSync™ Multichip Synchronization n –229dBc/Hz Normalized In-Band Phase Noise Floor n –281dBc/Hz Normalized In-Band 1/f Noise n Eleven Independent, Low Noise Outputs with Programmable Coarse Digital and Fine Analog Delays n Flexible Outputs Can Serve as Either a Device Clock or SYSREF Signal n Reference Input Frequency up to 500MHz n LTC6952Wizard™ Software Design Tool Support n –40ºC to 125°C Operating Junction Temperature Range n High Performance Data Converter Clocking n Wireless Infrastructure n Test and Measurement All registered trademarks and trademarks are the property of their respective owners. Protected by U.S. Patents, including 8319551 and 8819472. LTC6952 Phase Noise 33nF 22nF 48.7Ω 1.2µF 48.7Ω 49.9Ω 1µF 1µF 0.1µF 75Ω 30Ω 0.1µF 100Ω 1µF 0.1µF 0.1µF 100Ω 0.47µF CP Pascal OCXO-E 100MHz Ref Osc Crystek CVCO55CC- 4000-4000 VCO+ VCO– REF+ REF– VOUT + VREF + VD+ VCP + 3.3V 5V Vtune VVCO + LTC6952 LTC6952Wizard REGISTER VALUES: FILE: LTC6952 EZSync STANDALONE 3.3V EZS_SRQ+ EZS_SRQ– OUTx+ OUTx– TO SYNC OUTPUTS: TOGGLE SSYNC REGISTER BIT 6952 TA01a 12.5MHz ADC SYSREF 500MHz ADC CLOCK 500MHz ADC CLOCK 4GHz DAC CLOCK 4GHz DAC CLOCK 125MHz FPGA CLOCK 100MHz FPGA MGMT CLOCK OUT10± OUT6± OUT7± OUT8± OUT9± OUT0± OUT1± OUT2± OUT3± OUT4± OUT5± 12.5MHz ADC SYSREF 12.5MHz FPGA SYSREF 12.5MHz DAC SYSREF 12.5MHz DAC SYSREF OUTPUT TERMINATION DETAIL RMS JITTER = 65fs EQUIVALENT ADC SNR METHOD NOTES 10, 13 4GHz 500MHz OFFSET FREQUENCY (Hz) 1k 10k 100k 1M 10M 40M –170 –160 –150 –140 –130 –120 –110 –100 6952 TA01b Document Feedback |
Аналогичный номер детали - LTC6952 |
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Аналогичное описание - LTC6952 |
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