LTC6952 datasheet(69/80 Pages) AD

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LTC6952

6952f

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Preliminary Technical Data

Advance Product Information Subject to Change

Rev PrA

MEASURING CLOCK JITTER INDIRECTLY USING ADC SNR

Forsomeapplications,integratingaclockgenerator’sphase

noise within a defined offset frequency range (i.e. 12kHz to

20MHz) is sufficient to calculate the clock’s impact on the

overall system performance. In these situations, the RMS

jitter can be calculated from a phase noise measurement.

However, other applications require knowledge of the

clock’s phase noise at frequency offsets that exceed the

capabilities of today’s phase noise analyzers. This limita-

tion makes it difficult to calculate jitter from a phase noise

measurement.

The RMS jitter of an ADC clock source can be indirectly

measured by comparing a jitter dominated SNR measure-

ment to a non-jitter dominated SNR measurement. A jitter

dominated SNR measurement (SNRJITTER) is created by

applying a low jitter, high frequency full-scale sinewave

to the ADC analog input. A non-jitter dominated SNR

measurement (SNRBASE) is created by applying a very low

amplitude (or low frequency) sinewave to the ADC analog

input. The total clock jitter (tJ(TOTAL)) can be calculated

using Equation 25.

TJ(TOTAL) =

log

10 10

–

SNRJITTER

⎛

⎝

⎜

⎞

⎠

⎟

–10

–

SNRBASE

⎛

⎝

⎜

⎞

⎠

⎟

⎡

⎣

⎢

⎤

⎦

⎥

πfIN

(25)

Assuming the inherent aperture jitter of the ADC (tJ(ADC)) is

known, the jitter of the clock generator (tJ(CLK)) is obtained

using Equation 23.

ADC SAMPLE CLOCK INPUT DRIVE REQUIREMENTS

Modern high speed, high resolution ADCs are incredibly

sensitive components able to match or exceed labora-

tory instrument performance in many regards. Noise or

interfering signals on the analog signal input, the voltage

reference or the sampling clock input can easily appear

in the digitized data. To deliver the full performance of

any ADC, the sampling clock input must be driven with a

clean, low jitter signal.

APPLICATIONS INFORMATION

Figure 45 shows a simplified version of a typical ADC

sample clock input. In this case the input pins are labeled

ENC± for Encode while some ADCs label the inputs CLK±

for Clock. The input is composed of a differential limiting

amplifier stage followed by a buffer that directly controls

the ADC’s track and hold stage.

6952 F45

VDD

1.2V

10k

ENC+

ENC–

Figure 45. Simplified Sample Clock Input Circuit

The sample clock input amplifier also benefits from a fast

slewing input signal as the amplifier has noise of its own. By

slewing through the crossover region quickly, the amplifier

noise creates less jitter than if the transition were slow.

As shown in Figure 45, the ADC’s sample clock input is

typically differential, with a differential sampling clock

delivering the best performance. Figure 45 also shows

the sample clock input having a different common mode

input voltage than the LTC6952’s CML outputs. Most ADC

applications will require AC coupling to convert between

the two common mode voltages.

TRANSMISSION LINES AND TERMINATION

Interconnection of high speed signaling with fast rise

and fall times requires the use of transmission lines with

properly matched termination. The transmission lines may

be stripline, microstrip or any other design topology. A

detailed discussion of transmission line design is beyond

the scope of this data sheet. Any mismatch between the

transmission line’s characteristic impedance and the

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