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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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LTC6952 датащи(PDF) 6 Page - Analog Devices |
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LTC6952 датащи(HTML) 6 Page - Analog Devices |
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6 / 80 page  LTC6952 6 6952f For more information www.analog.com Preliminary Technical Data Advance Product Information Subject to Change Rev PrA SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Output Hi-Z Leakage Current ICP = 420µA (Note 7) 0.5 nA ICP = 11.2mA (Note 7) 5 nA VMID Mid-supply Output Bias Ratio Referred to (VCP+ - GND) 0.48 V/V Reference Divider (R) R Divide Range All Integers Included l 1 1023 Counts VCO Divider (N) N Divide Range All Integers Included l 1 65535 Counts Digital Pin Specifications VIH High-level Input Voltage CS, SDI, SCLK, SD l 1.55 V VIL Low-level Input Voltage CS, SDI, SCLK, SD l 0.8 V VIHYS Input Voltage Hysteresis CS, SDI, SCLK, SD 250 mV Input Current CS, SDI, SCLK, SD l ±1 µA IOH High-level Output Current SDO and STAT, VOH = VD+ - 400mV l –3.3 –1.9 mA IOL Low-level Output Current SDO and STAT, VOL = 400mV l 2.0 3.4 mA SDO Hi-Z Current l ±1 µA Digital Timing Specifications tCKH SCLK High Time l 25 ns tCKL SCLK Low Time l 25 ns tCSS CS Setup Time l 10 ns tCSH CS High Time l 10 ns tCS SDI to SCLK Setup Time l 6 ns tCH SDI to SCLK Hold Time l 6 ns tDO SCLK to SDO Time To VIH/VIL/Hi-Z with 30pF load l 16 ns EZS_SRQ Timing Specifications (See Figure 2) tSRQH EZS_SRQ High Time l 1 ms tSRQL EZS_SRQ Low Time l 1 ms EZS_SRQ Skew, Part to Part SRQMD = 0, PARSYNC = 0 10 µs tSS EZS_SRQ to REF Setup Time PARSYNC = 1, CMOS EZS_SRQ l 1 ns PARSYNC = 1, Differential EZS_SRQ l TBD tSH EZS_SRQ to REF Hold Time PARSYNC = 1, CMOS EZS_SRQ l 1 ns PARSYNC = 1, Differential EZS_SRQ l TBD Output Dividers (M0, M1, M2, M3, M4, M5, M6, M7, M8, M9 and M10) Mx Output Divider Range (x = 0 to 10) Mx = P × 2N, where P = 1 to 32 all integers, N = 0 to 7 l 1 4096 Counts DDELx Output Digital Delay (x = 0 to 10) ½ VCO Cycles (Note 3) l 0 4095 ½ Cycles tADELx Output Analog Delay Time (x = 0 to 10) ADELx = 0 0 ps ADELx = 1, fOUTx ≤ 300MHz 90 ADELx = 63, fOUTx ≤ 300MHz 1100 Output Analog Delay Time (x = 0 to 10), Step Size ADELx = 1 to 31, fOUTx ≤ 300MHz 11 ps ADELx = 32 to 63, fOUTx ≤ 300MHz 26 Output Analog Delay (x = 0 to 10) 300MHz ≤ fOUTx ≤ 2.25GHz Note 4 Maximum Output Frequency for Analog Delay 2.25 GHz Temperature Coefficient of Analog Delay Time ADELx = 1 to 31 l 0.06 %/°C ADELx = 32 to 63 l 0.06 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at TA = 25°C. VREF+ = VD+ = VVCO+ = VOUT+ = 3.3V, VCP+ = 5V unless otherwise specified (Note 2). All voltages are with respect to GND. |
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