LTC6952 datasheet(71/80 Pages) AD

71 / 80 page

LTC6952

6952f

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Preliminary Technical Data

Advance Product Information Subject to Change

Rev PrA

APPLICATIONS INFORMATION

USING THE LTC6952 TO DRIVE AC COUPLED SYSREF

INPUTS IN CONTINUOUS OR GATED MODE

Some converters cannot accept a 2.3V common mode

CML signal. In this situation, the SYSREF must be AC

coupled. AC coupling complicates the usage of SYSREF

since it is generally not continuously operational, lead-

ing to long settling time requirements before a SYSREF

is requested. However, AC coupling on SYSREF can be

accomplished by using the connections shown in Figure

49 for continuous or gated SYSREF pulses (MODEx = 0

or 1). Note that some receiver devices have the 100Ω

termination resistor internal to the part, in which case the

external 100Ω resistor is unnecessary for continuous or

gated SYSREFs.

Continuous or Gated SYSREFs (MODEx = 0 or 1)

1. Enable the LTC6952 SYSREF output drivers by setting

PDx = 0 and set SRQMD = 1.

2. If gated SYSREFs (MODEx = 1) are being used, set

SSRQ or the EZS_SRQ inputs to “1”.

3. Wait for a settling period of at least tsettleC.

4. Set the receiver device to accept SYSREFs.

5. After the SYSREFs have been accepted by the receiver

device, set the device to stop accepting SYSREFs.

6. If gated SYSREFs (MODEx = 1) are being used, set

SSRQ or the EZS_SRQ inputs to “0”.

7. Disable the LTC6952 SYSREF output drivers by setting

PDx = 2 and set SRQMD = 0.

USING THE LTC6952 TO DRIVE AC COUPLED SYSREF

INPUTS IN PULSED MODE

If AC coupling is required for pulsed SYSREF applications

(MODEx = 3), the connections shown in Figure 50 can be

used. Note that some receiver devices have the 100Ω ter-

mination resistor internal to the part. In this situation, the

use of AC coupled, pulsed SYSREFs is not recommended.

RDIFF/2

RCM

100Ω

CAC

ADC, DAC, or FPGA

SYSREF+

SYSREF–

VCM

OUTx+

OUTx–

LTC6952

VDD

6952 F50

100Ω

CAC

RDIFF/2

RCM

6952 F49

OUTx+

OUTx–

LTC6952

ADC, DAC, or FPGA

SYSREF+

SYSREF–

VCM

Settling time for continuous or gated SYSREF connections

is determined by the AC coupling capacitors (CAC), and

both the differential and common mode input resistances

of the receiver device (RDIFF and RCM):

tsettleC ≅ 10 • (2RCM + RDIFF/2) • CAC

Use the following procedure to achieve correct JESD204B

SYSREF behavior for AC coupled continuous or gated

SYSREFs.

These methods assume that the SYSREF outputs have

already been synchronized and that the SYSREF output

drivers have been disabled for power savings (PDx = 2).

Figure 49. OUTx CML AC Coupled Connections to SYSREF Inputs

for Continuous or Gated Mode Operation

Figure 50. OUTx CML AC Coupled Connections to SYSREF Inputs

for Pulsed Mode Operation

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