LTC6952 datasheet(28/80 Pages) AD

28 / 80 page

LTC6952

6952f

For more information www.analog.com

Preliminary Technical Data

Advance Product Information Subject to Change

Rev PrA

The SYNC/SRQ timing for ParallelSync can be simpli-

fied to a single software bit write by using an LTC6953

(or LTC6952 with its PLL disabled) as the reference and

EZS_SRQ distribution block, as shown in Figure 14. In

this application, the EZS_SRQ outputs of the reference

distribution part should be set to transition on the fall-

ing edge of its corresponding reference clock output. To

achieve this, first synchronize the reference distribution

part using the settings given in Table 18, where DDELREF

can be any valid DDEL value.

Just before sending a SYNC or SYSREF request to the par-

allel parts, set the reference distribution part’s SRQMD bit

to “1”. This will automatically retime the passed-through

requests to the reference clocks. After the request is done,

set the SRQMD bit back to “0” to save supply current

from the reference distribution part. See the Applications

Information section for a programming example.

Table 18. Reference Distribution Divider and DDEL Settings for

ParallelSync

REF CLK

Divide

REF CLK

DDEL

EZS_SRQ

Divide

EZS_SRQ

DDEL

DDELREF

DDELREF+1

DDELREF

DDELREF+2

DDELREF

DDELREF+3

DDELREF

DDELREF+4

REF Divide >4

DDELREF

=REF Divide

DDELREF

Part-to-part skew in a ParallelSync application can be

minimized by setting the RAO bit in register h06 to “1”.

RAO stands for “reference aligned output”, and it aligns

internal delays such that the output rising edge will always

occur at an exact integer number of VCO clock cycles from

the incoming reference signal. The trade-off for using the

RAO mode is slightly degraded PLL in-band noise (<1.0dB).

To determine the best configuration for a given application,

the flowchart in Figure 15 can be used. This flowchart

uses the parameters from Table 17 to guide the user to

the most suitable configuration.

OPERATION

100Ω

OUTx±

EZS_SRQ+

REF+

OUT0+

OUT1+

EZS_SRQ+

EZS_SRQ–

OUT10+

OUT2+

OUT3+

OUT4+

OUT5+

OUT6+

OUT7+

OUT8+

OUT9+

LTC6952

11 OUTPUTS

VCO±

REF IN

LTC6953 or

LTC6952

REFERENCE

DISTRIBUTION

OUT0–

REF–

LTC6952

OUT1–

OUTx±

LTC6952

11 OUTPUTS

LTC6952

OUT2–

OUT3–

OUTx±

11 OUTPUTS

OUTx±

11 OUTPUTS

OUT4–

OUT5–

OUT6–

OUT7–

OUTx±

11 OUTPUTS

LTC6952

OUT10–

OUT8–

OUT9–

EZS_SRQ–

EZS_SRQ+

EZS_SRQ–

EZS_SRQ+

EZS_SRQ–

EZS_SRQ+

EZS_SRQ–

EZS_SRQ+

EZS_SRQ–

1 OUTPUT

EZS_SRQ CONNECTIONS

MUST BE DC COUPLED

LF(s)

VCO±

VCO

LF(s)

VCO±

VCO

LF(s)

VCO±

VCO

LF(s)

VCO±

VCO

LF(s)

VCO±

VCO

REF+

REF–

REF+

REF–

REF+

REF–

REF+

REF–

6952 F14

SYNC OR

SYSREF

REQUEST:

TOGGLE PIN

OR WRITE

SSRQ BIT

Figure 14. ParallelSync Multi-Chip Synchronization

with LTC6953 or LTC6952 Reference Distribution

Depending on the user’s system requirements, many

simplifications or additions can be made for multiple chip

synchronization. For example, the above applications only

assume a maximum of two stages, even though more

stages can be added to increase the number of outputs.

However, these applications are beyond the scope of this

data sheet. Please contact the factory.

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