LTC6952 datasheet(22/80 Pages) AD

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LTC6952

6952f

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Preliminary Technical Data

Advance Product Information Subject to Change

Rev PrA

Figure 7 shows the approximate analog delay time (tADELx)

vs ADELx and output frequency. Note that the y-axis is

logarithmic scale, and that analog delay is zero for ADEL = 0.

See the Applications Information section for a more com-

prehensive method of calculating expected analog delay.

OPERATION

< 300MHz

500MHz

750MHz

1GHz

1.5GHz

1.75GHz

2.25GHz

ADEL CODE

160

320

640

1280

6952 F07

Figure 7. Analog Delay vs ADEL Code and Output Frequency

Figure 8. Simplified CML Interface Schematic (All OUTx)

Use caution when using analog delay on device clocks

as this will degrade jitter. Digital delay should be used

whenever possible since it does not impact performance.

The maximum value of analog delay will never need to be

more than half of a VCO input period.

Analog delays are always enabled regardless of the value

of the SRQENx bits, and they take effect immediately upon

a write to the ADELx registers. However, changes in ADEL

can cause the output to glitch temporarily, especially

switching between ADEL=0 and ADEL≠0. See the Appli-

cations Information section for details on the use of the

analog delay settings. The LTC6952Wizard may be used

for ADEL calculation and visualization.

CML OUTPUT BUFFERS (OUT0 TO OUT10)

All of the outputs are very low noise, low skew 2.5V CML

buffers. Each output can be either AC or DC coupled, and

terminated with 100Ω differentially. If a single-ended output

is desired, each side of the CML output can be individually

AC coupled and terminated with 50Ω. The OINVx bits can

selectively invert the sense of each output to facilitate board

routing without having to cross matched length traces.

OINVx also determines the state of the output in a muted

VOUT

OUTx+

33Ω

50Ω

OUTx–

6952 F08

OUTPUT SYNCHRONIZATION AND SYSREF GENERATION

The LTC6952 has circuitry to allow all outputs to be

synchronized into known phase alignments in multiple

ways to suit different applications using the EZSync and

ParallelSync Multichip Clock Edge Synchronization pro-

tocols. Synchronization can be between any combination

of outputs on the same chip (EZSync Standalone), across

multiple cascaded follower chips (EZSync Multi-Chip), or

even across multiple parallel chips on the same reference

domain (ParallelSync). Once the outputs are at the correct

frequency and synchronized, the LTC6952 also has the

ability to produce free-running, gated, or finitely pulsed

SYSREF signals as indicated by the JESD204B subclass 1

specification.

EZS_SRQ Input Buffer

Both synchronization and SYSREF requests are achieved

by either a software signal (bit SSRQ in register h0B) or

a voltage signal on the EZS_SRQ± pins. The voltage on

these pins may be any differential signal within the speci-

fications in the Electrical Characteristics, or alternatively

a CMOS signal on EZS_SRQ+ while EZS_SRQ– is tied to

GND. A simplified schematic of the EZS_SRQ input is

shown in Figure 9. When using the SSRQ bit, the state of

the EZS_SRQ± pins must be a logic “0”, easily achieved

by setting both EZS_SRQ± pins to GND. Likewise, when

using the EZS_SRQ± pins, bit SSRQ must be set to “0”.

Table 12 shows the use of the EZS_SRQ± pins and SSRQ

bit vs the SRQMD and PARSYNC bits. SSRQ bit control

condition (PDx = 1) as shown in Table 10. See Figure 8

for circuit details.

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