LTC6952 datasheet(20/80 Pages) AD

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LTC6952

6952f

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Preliminary Technical Data

Advance Product Information Subject to Change

Rev PrA

Table 7. Charge Pump Function Bit Descriptions

BIT

DESCRIPTION

CPDN

Force Sink Current

CPINV

Invert PFD Phase

CPMID

Enable Mid-Voltage Bias

CPRST

Reset PFD, Hi-Z CP

CPUP

Force Source Current

CPWIDE

Extend Current Pulse Width

The CPMID bit found in register h0B enables a resistive

VCP+/2 output bias which may be used to pre-bias trouble-

some loop filters into a valid voltage range. When using

CPMID, it is recommended to also assert the CPRST

bit, forcing a PFD reset which puts the charge pump in

a Hi-Z state. Both CPMID and CPRST must be set to “0”

for normal operation.

The CPUP and CPDN bits force a constant ICP source or

sink current, respectively, on the CP pin. The CPRST bit

may also be used in conjunction with the CPUP and CPDN

bits, allowing a pre-charge of the loop to a known state,

if required. CPUP, CPDN, and CPRST must be set to “0”

to allow the loop to lock.

The CPWIDE bit extends the charge pump output cur-

rent pulse width by increasing the PFD reset path’s delay

value. CPWIDE is normally set to “0”. Setting CPWIDE =

0 provides the best in-band phase noise performance.

The CPINV bit found in register h0B should be set for ap-

plications requiring signal inversion from the PFD, such

as for loops using negative-slope tuning oscillators or

for complex external loops using an inverting op amp in

conjunction with a positive-slope tuning oscillator. A pas-

sive loop filter used in conjunction with a positive-slope

VCO requires no inversion, so CPINV = 0.

REFERENCE ALIGNED OUTPUT (RAO) MODE

The RAO mode is activated by setting the RAO bit in register

h06 to “1”. It aligns internal delays such that the output

rising edge will always occur at an exact integer number

of VCO clock cycles from the incoming reference signal.

This mode is only used for closed loop PLL applications

(PDPLL = 0), and is useful when a known delay between

outputs and the incoming reference signal is required. It

is also used to minimize skew between parallel LTC6952s

OPERATION

in ParallelSync applications (see the ParallelSync section).

The tradeoff for using the RAO mode is slightly degraded

PLL in-band noise (<0.5dB).

VCO INPUT BUFFER

The LTC6952’sVCOinputbufferprovidesaflexibleinterface

to either differential or single-ended frequency sources.

The inputs are self-biased, and AC-coupling is recom-

mended for applications using external VCO/VCXO/VCSOs.

However, the VCO input can also be driven DC-coupled by

LVPECL, CML, or any other driver type within the input’s

specified common mode range. See the Applications In-

formation section for more information on common VCO

input interface configurations, noting that the LTC6952’s

VCO input buffer has an internal differential resistance of

250Ω as shown in Figure 6.

BIAS

2.1V

935Ω

125Ω

FILTV

6952 F06

125Ω

VCO+

VCO–

VVCO

Figure 6. Simplified VCO Interface Schematic

The maximum input frequency for the VCO buffer is 4.5GHz,

and the maximum amplitude is 1.6VP-P. It is also important

that the VCO± input signal be low noise and have a slew

rate of at least 100V/µs, although better performance will

be achieved with a higher slew rate. For applications with

VCO input slew rates less than 2V/ns, better phase noise

performance will be achieved by enabling the internal broad-

band noise filtering circuit within the VCO input buffer. This

is accomplished by asserting the configuration bit FILTV in

serial port register h02. Note that setting FILTV = 1 when the

slew rate of the VCO input is greater than 2V/ns will degrade

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