LTC6952 datasheet(13/80 Pages) AD

13 / 80 page

LTC6952

6952f

For more information www.analog.com

Preliminary Technical Data

Advance Product Information Subject to Change

Rev PrA

PIN FUNCTIONS

CS (Pin 1): Serial Port Chip Select. This CMOS input initi-

ates a serial port communication burst when driven low,

ending the burst when driven back high. See the Operation

section for more details.

VD+ (Pin 2): 3.15V to 3.45V positive supply pins for syn-

chronization/SYSREF request functions and serial port.

This pin should be bypassed directly to the ground plane

using a 0.01µF ceramic capacitor as close to the pin as

possible.

OUT0+, OUT0– (Pins 34, 33): Output Signals. The output

divider is buffered and presented differentially on these

pins. The outputs have 50Ω (typical) output resistance per

side (100Ω differential). The far end of the transmission

line is typically terminated with 100Ω connected across the

outputs. See the Operation and Applications Information

section for more details.

OUT1+, OUT1– (Pins 31, 30): Same as OUT0.

OUT2+, OUT2– (Pins 28, 27): Same as OUT0.

OUT3+, OUT3– (Pins 25, 24): Same as OUT0.

OUT4+, OUT4– (Pins 22, 21): Same as OUT0.

OUT5+, OUT5– (Pins 19, 18): Same as OUT0.

OUT6+, OUT6– (Pins 16, 15): Same as OUT0.

OUT7+, OUT7– (Pins 13, 12): Same as OUT0.

OUT8+, OUT8– (Pins 10, 9): Same as OUT0.

OUT9+, OUT9– (Pins 7, 6): Same as OUT0.

OUT10+, OUT10– (Pins 4, 3): Same as OUT0.

VOUT+ (Pins 5, 8, 11, 14, 17, 20, 23, 26, 29, 32, 35):

3.15V to 3.45V positive supply pins for output dividers.

Each pin should be separately bypassed directly to the

ground plane using a 0.01µF ceramic capacitor as close

to the pin as possible.

NC (Pin 36): Not Connected Internally. It is recommended

that this pin be connected to the ground pad (Pin 53).

VCO+, VCO– (Pins 37, 38): VCO Input Signals. The dif-

ferential signal placed on these pins is buffered with a low

noise amplifier and fed to the internal distribution path

and feedback dividers. These self-biased inputs present

a differential 250Ω (typical) resistance to aid impedance

matching. They may also be driven single-ended by using

the matching circuit in the Applications Information section.

VVCO+ (Pins 39): 3.15V to 3.45V positive supply pin for

VCO circuitry. This pin should be bypassed directly to the

ground plane using a 0.01µF ceramic capacitor as close

to the pin as possible.

SD (Pin 40): Chip Shutdown Pin. When tied to GND, this

CMOS input disables all blocks in the chip. This is the

same function as PDALL in the serial interface.

GND (Pin 41): Negative Power Supply (Ground). This pin

should be tied directly to the ground pad (Pin 53).

VCP+(Pin42):3.15Vto5.25Vpositivesupplypinforcharge

pump circuitry. This pin should be bypassed directly to

the ground plane using a 0.1µF ceramic capacitor as close

to the pin as possible.

CP (Pin 43): Charge Pump Output. This bidirectional cur-

rent output is normally connected to the external loop filter.

See the Applications Information section for more details.

VREF+ (Pin 44):3.15V to 3.45Vpositive supply pin for refer-

ence input circuitry. This pin should be bypassed directly

to the ground plane using a 0.1µF ceramic capacitor as

close to the pin as possible.

REF+, REF– (Pins 45, 46): Reference Input Signals. This

differential input is buffered with a low noise amplifier,

which feeds the reference divider. They are self-biased and

must be AC coupled with 1µF capacitors. If used single-

ended with V(REF+) ≤ 2.7VP-P, bypass REF– to GND with

a 100nF capacitor. If used single-ended with V(REF+) >

2.7VP-P, bypass REF– to GND with a 47pF capacitor.

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