LTC6952 datasheet(21/80 Pages) AD

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LTC6952

6952f

For more information www.analog.com

Preliminary Technical Data

Advance Product Information Subject to Change

Rev PrA

OPERATION

the overall PLL phase noise performance. See Table 8 for

recommended settings of FILTV.

Table 8. FILTV Programming

FILTV

Slew Rate of VCO Input

< 2V/ns

≥ 2V/ns

VCO Peak Detector

A VCO input peak detection circuit is provided on the VCO±

inputs to detect the presence of a VCO signal and provides

the VCOOK and VCOOK status flags available through both

the STAT output and serial port register h00. VCOOK is

the logical inverse of VCOOK. The circuit has hysteresis to

prevent the VCOOK flag from chattering at the detection

threshold. The reference peak detector may be powered-

down using the PDVCOPK bit found in register h02.

The peak detector approximates an RMS detector, therefore

sine and square wave inputs will give different detection

thresholds by a factor of 4/π. See Table 9 for VCOOK

detection values.

Table 9. VCOOK, VCOOK Status Output vs VCO Input

VCOOK

Sine Wave fVCO

Square Wave fVCO

≥ 350mVP–P

≥ 275mVP–P

< 100mVP–P

< 75mVP–P

VCO DIVIDER (N)

The 16-bit N divider provides the feedback from the ex-

ternal VCO to the PFD. The divide ratio may be directly

programmed from 1 to 65535 using the ND[15:0] bits

found in registers h08 and h09. See the Applications

Information section for the relationship between N and

the fREF, fPFD, and fVCO frequencies.

OUTPUT DIVIDERS (M0 TO M10)

The eleven independent, identical output dividers are driven

directly from the VCO input buffer. They divide the incoming

VCO frequency fVCO by the divide value Mx to produce a

50% duty cycle output signal at frequency fOUTx. The Mx

value is set by the MPx[4:0] and the MDx[2:0] bits using

the following equation:

Mx = (MPx + 1) • 2MDx

(1)

For proper operation, MDx must be 0 if Mx is less than

or equal to 32.

Any divider can be muted or powered down to save current

by adjusting its corresponding PDx[1:0] bits. The descrip-

tion of the PDx[1:0] bits is shown in Table 10.

Table 10. PDx[1:0] Programming

PDx[1:0]

DESCRIPTION

Normal Operation

Mute Output (OUTx=0 if OINVx=0, OUTx=1 if OINVx=1),

Internal Divider Remains Running and Synchronized

Power Down Output (Both + and – Outputs Go to VOUT+),

Internal Divider Remains Running and Synchronized

Power Down Divider and Output (Both + and – Outputs

Go to VOUT+), Internal Divider Stops and Must Be Re-

Synchronized Upon Return to Normal Operation

DIGITAL OUTPUT DELAYS (DDEL0 TO DDEL10)

Each output divider can have the start time of the output

delayed by integer multiples of ½ of the VCO period after

a synchronization event. The digital delay value is pro-

grammed into the DDELx[11:0] bits and can be any value

from 0 to 4095. Digital delays are only enabled when

the synchronization bits SRQENx are set to “1”, and any

changes to the output digital delays will not be reflected

until after synchronization. Digital delay can be used with no

degradation to clock jitter performance. See the Operation

sectiononSynchronizationandtheApplicationsInformation

section for details on the use of the digital delay settings.

ANALOG OUTPUT DELAYS (ADEL0 TO ADEL10)

Each output has a fine analog delay feature to further adjust

its output delay time (tADELx)insmallstepscontrolledbythe

ADELx[5:0] bits. For output frequencies less than 300MHz,

absolute time delays range from 0 to 1.1ns. Above 300MHz,

the time delay is output frequency dependent, and the valid

useful range of ADELx is reduced according to Table 11.

Table 11. Maximum ADELx vs Output Frequency Range

fOUT Range

Maximum ADELx

fOUTx ≤ 750MHz

750MHz < fOUTx ≤ 1GHz

1GHz < fOUTx ≤ 1.5GHz

1.5GHz < fOUTx ≤ 1.75GHz

1.75GHz < fOUTx ≤ 2.25GHz

fOUTx > 2.25GHz

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