LTC6952 datasheet(63/80 Pages) AD

63 / 80 page

LTC6952

6952f

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Preliminary Technical Data

Advance Product Information Subject to Change

Rev PrA

APPLICATIONS INFORMATION

Parallel LTC6952 Synchronization

The outputs of the parallel LTC6952s in this example are

now running at the desired frequency, but have random

phase relationships with each other. Synchronization forces

the outputs to run at known and repeatable phases and can

be achieved in this example either externally, by driving

the REF LTC6953’s EZS_SRQ± pins, or internally, with the

REF LTC6953’s SSRQ bit in Reg0B. For this example, use

the SSRQ bit and hold the EZS_SRQ± pins low:

REF LTC6953 Reg0B = h05

After waiting a minimum of 1ms, write Reg0B again:

REF LTC6953 Reg0B = h04

Once the internal synchronization process completes, the

outputs will be aligned as shown in Figure 36. Note that the

internal divider behavior for the muted SYSREF outputs

is shown as well as the actual outputs to demonstrate the

phase alignment following synchronization.

Putting the ICs into a Low Power Mode (Optional)

If desired, the ICs can be placed into lower power modes

while awaiting a SYSREF request. This is achieved by set-

ting PDx = 2 for all SYSREF-defined outputs. This powers

down the output driver circuitry but leaves the internal

divider running and in the correct phase relationship to

the clocks.

ADC DEVICE CLOCKS

(OUT1, 3, 5 AND 7)

ADC DEVICE CLOCKS

(OUT4, 6, 8 AND 10)

EZS_SRQ OR SSRQ BIT

ON REFERENCE LTC6953

REF LTC6953 OUTPUTS

LTC6952 #1 OUTPUTS

LTC6952 #2 OUTPUTS

ADC SYSREFs

(MUTED OUT0, 2, 4 AND 6)

ADC SYSREFs

(MUTED OUT3, 5, 7 AND 9)

FPGA SYSREF

(MUTED OUT1)

FPGA DEVICE CLOCK

(OUT2)

SYSREF VALID CLOCK EDGE

NOT SYNCHRONIZED, PHASE UNDETERMINED

6952 F36

FPGA MANAGEMENT CLOCK

(OUT10)

INTERNAL ADC SYSREF DIVIDERS

(MUTED OUT0, 2, 4 AND 6)

INTERNAL ADC SYSREF DIVIDERS

(MUTED OUT3, 5, 7 AND 9)

INTERNAL FPGA SYSREF DIVIDER

(MUTED OUT1)

REFERENCE CLOCKS

(OUT0 AND 2)

SRQ PASSTHROUGH

(OUT1 and 3)

Figure 36. Outputs after Synchronization for the ParallelSync Design Example (SRQMD=0)

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