LTC6952 datasheet(2/80 Pages) AD

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LTC6952

6952f

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Preliminary Technical Data

Advance Product Information Subject to Change

Rev PrA

TABLE OF CONTENTS

Features ............................................................................................................................ 1

Applications ....................................................................................................................... 1

Typical Application ............................................................................................................... 1

Description......................................................................................................................... 1

Absolute Maximum Ratings..................................................................................................... 4

Pin Configuration ................................................................................................................. 4

Electrical Characteristics ........................................................................................................ 5

Typical Performance Characteristics .......................................................................................... 9

Pin Functions .....................................................................................................................13

Block Diagram....................................................................................................................15

Timing Diagrams ................................................................................................................16

Operation..........................................................................................................................17

Reference Input Buffer.......................................................................................................................................... 17

Reference Divider (R) ........................................................................................................................................... 18

Phase/Frequency Detector (PFD) .......................................................................................................................... 18

Lock Indicator....................................................................................................................................................... 18

Charge Pump........................................................................................................................................................ 19

Reference Aligned Output (RAO) Mode ................................................................................................................ 20

VCO Input Buffer................................................................................................................................................... 20

VCO Divider (N) .................................................................................................................................................... 21

Output Dividers (M0 to M10)................................................................................................................................ 21

Digital Output Delays (DDEL0 to DDEL10)............................................................................................................ 21

Analog Output Delays (ADEL0 to ADEL10) ........................................................................................................... 21

CML Output Buffers (OUT0 to OUT10) ................................................................................................................. 22

Output Synchronization and SYSREF Generation.................................................................................................. 22

Serial Port............................................................................................................................................................. 30

Block Power-Down Control ................................................................................................................................... 36

Applications Information .......................................................................................................37

Introduction .......................................................................................................................................................... 37

Output Frequency ................................................................................................................................................. 37

Loop Filter Design................................................................................................................................................. 37

Digital and Analog Output Delays.......................................................................................................................... 38

Reference Input .................................................................................................................................................... 38

VCO Input ............................................................................................................................................................. 38

EZS_SRQ Input..................................................................................................................................................... 41

JESD204B Design Example Using EZSync Standalone ......................................................................................... 41

JESD204B Design Example Using Ezsync Multi-Chip ........................................................................................... 48

Reference Source Considerations ......................................................................................................................... 64

In-Band Output Phase Noise................................................................................................................................. 65

Output Phase Noise Due To 1/f Noise ................................................................................................................... 65

Reference Signal Routing, Spurious, and Phase Noise......................................................................................... 65

Supply Bypassing and PCB Layout Guidelines...................................................................................................... 66

ADC Clocking and Jitter Requirements ................................................................................................................. 67

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