LTC6952 datasheet(67/80 Pages) AD

67 / 80 page

LTC6952

6952f

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Preliminary Technical Data

Advance Product Information Subject to Change

Rev PrA

grounding for electrical and thermal performance can be

found on the DC2609 layout.

ADC CLOCKING AND JITTER REQUIREMENTS

Adding noise directly to a clean signal clearly reduces its

signal to noise ratio (SNR). In data acquisition applica-

tions, digitizing a clean signal with a noisy clock signal

also degrades the SNR. This issue is best explained in

the time domain using jitter instead of phase noise. For

this discussion, assume that the jitter is white (flat with

frequency) and of Gaussian distribution.

Figure 42 shows a sine wave signal entering a typical data

acquisition circuit composed of an ADC, an input signal

amplifier and a sampling clock. Also shown are three

signal sampling scenarios for sampling the sine wave at

its zero crossing.

In the first scenario, a perfect sine wave input is buffered

by a noiseless amplifier to drive the ADC. Sampling is

performed by a perfect, zero jitter clock. Without any added

APPLICATIONS INFORMATION

noise or sampling clock jitter, the ADC’s digitized output

value is very clearly determined and perfectly repeatable

from cycle to cycle.

In the second scenario, a perfect sine wave input is buff-

ered by a noisy amplifier to drive the ADC. Sampling is

performed by a perfect, zero jitter clock. The added noise

results in an uncertainty in the digitized value, causing an

error term which degrades the SNR. The degraded SNR in

this scenario, from adding noise to the signal, is expected.

In the third scenario, a perfect sine wave input is buffered

by a noiseless amplifier to drive the ADC. Sampling is

performed by a clock signal with added jitter. Note that

as the signal is slewing, the jitter of the clock signal leads

to an uncertainty in the digitized value and an error term

just as in the previous scenario. Again, this error term

degrades the SNR.

A real-world system will have both additive amplifier noise

and sample clock jitter. Once the signal is digitized, deter-

mining the root cause of any SNR degradation – amplifier

noise or sampling clock jitter – is essentially impossible.

6952 F42

SINE WAVE

INPUT SIGNAL WITH

NOISELESS AMP

SAMPLING CLOCK WITH ADDED JITTER

∆V = VERROR

SINE WAVE

INPUT SIGNAL WITH

NOISY AMP

SINE WAVE

INPUT SIGNAL

PERFECT SAMPLING CLOCK

∆V = VERROR

SINE WAVE

INPUT SIGNAL WITH

NOISELESS AMP

PERFECT SAMPLING CLOCK

VSAMPLE

SAMPLING CLOCK

BITS

ADC

AMP

Figure 42. A Typical Data Acquisition Circuit Showing the Sampling Error Effects of a Noisy Amplifier and a Jittery Sampling Clock

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