LTC6952 datasheet(23/80 Pages) AD

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LTC6952

6952f

For more information www.analog.com

Preliminary Technical Data

Advance Product Information Subject to Change

Rev PrA

OPERATION

Figure 9. Simplified EZS_SRQ Interface Schematic

VREF

FILTR

BIAS

28kΩ

7kΩ

EZS_SRQ+

EZS_SRQ–

0.8V

CMOS

2.1V

6952 F09

Note that synchronization MUST be performed before a

SYSREF request. The synchronization must be repeated

only if the divider setting is changed, or if the divider is

powered down.

Table 12. Purpose of EZS_SRQ± pins and SSRQ bit

SRQMD

EZS_SRQ PINS

SSRQ BIT

PARSYNC=0

PARSYNC=1

PARSYNC=0

PARSYNC=1

Synchronization

Request

(SYNC)

Synchronization

Request

(SYNC)

Synchronization

Request

(SYNC)

Disabled

SYSREF

Request

(SYSREQ)

SYSREF

Request

(SYSREQ)

SYSREF

Request

(SYSREQ)

Disabled

Synchronization Overview

The goal of synchronization is to align all output dividers

on single or multiple LTC6952s (or other EZSync or Paral-

lelSync Analog Devices clock devices) into a known phase

relationship. At initial power-up, after a power-on reset

(POR), or any time the output divide values are changed,

the outputs will not be synchronized. Any changes to the

output digital delays (DDELx) will not be reflected until after

synchronization. Although the outputs will be at the correct

frequency without synchronization, the phases will have an

unknown relationship until a synchronization event occurs.

To enable synchronization on the LTC6952, the SRQMD

bit in register h0B must be set to “0”. Synchronization

begins either with the EZS_SRQ input driven to a high

state or by writing “1” to the SSRQ bit (only if PARSYNC

= 0). For any output with its SRQENx bit set to “1”, the

output divider will stop running and return to a logic “0”

state after an internal timing delay of greater than 100μs.

The EZS_SRQ input state or SSRQ bit must remain high

for a minimum of 1ms.

Additionally, if bit PARSYNC is set to “1” when the EZS_SRQ

input is driven high, the R divider for R ≥ 2 is reset as

shown in Figure 2 and explained in the Reference Divider

(R) section. This synchronizes the internal PFD reference

inputs on multiple parallel LTC6952s.

When the EZS_SRQ input is driven back low, or “0” is written

to the SSRQ bit (only if PARSYNC = 0), the synchronized

internal dividers will start after an initial latency dependent

on the settings of bits PDPLL and PARSYNC , as shown

in Table 13 and Table 14. Outputs with DDELx≠0 will be

delayed by an extra DDELx/2 VCO cycles. The behavior of

each output will be defined individually by the output’s cor-

responding SRQENx and MODEx bits also shown in Table

13 and Table 14. All dividers with the same DDELx delay

setting will have their output rising edge occur within the

skew times as defined in the Electrical Characteristics table.

The range of each delay is 0 to 4095 VCO half cycles and is

independent of the divide ratio setting of each divider. See

the Applications Information section for synchronization

programming examples. Additionally, the LTC6952Wizard

may be used to visualize these timing relationships.

SYSREF Generation Overview

The JESD204B subclass 1 specification describes a method

to align multiple data converter devices (ADCs or DACs)

in time and provide repeatable and programmable latency

across the serial link with a logic device (FPGA). The Local

Multi-Frame Clocks (LMFC) and internal clock dividers on

all devices in the system are synchronized by a pulse (or

pulse train) named SYSREF. Care must be taken to make

sure the SYSREF signal remains synchronized to the ADC,

DAC, and FPGA clocks and meets setup and hold timing

as specified by the devices.

is disabled when PARSYNC is “1” due to setup and hold

time requirements to the REF input.

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