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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TMS320VC5421 датащи(PDF) 13 Page - Texas Instruments |
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TMS320VC5421 датащи(HTML) 13 Page - Texas Instruments |
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13 / 104 page  Introduction 13 December 1999 − Revised October 2008 SPRS098D 2.3 Pin Assignments Figure 2−1 provides the pin assignments for the 144-pin low-profile quad flatpack (LQFP) package. Figure 2−2 illustrates the ball locations for the 144-pin ball grid array (BGA) package and is used in conjunction with Table 2−2 to locate signal names and ball grid numbers. 2.3.1 Pin Assignments for the PGE Package The TMS320VC5421PGE 144-pin low-profile quad flatpack (LQFP) is footprint- and pin-compatible with the 5420. Table 2−1 lists the pin number and associated signal name for both the multiplexed mode and the nonmultiplexed mode. PPA14 PPA15 VSS PPA16 PPA17 B_INT0 B_INT1 B_NMI IS B_GPIO2/BIO B_GPIO1 B_GPIO0 B_BFSR1 B_BDR1 CVDD VSS B_BCLKR1 B_BFSX1 VSS B_BDX1 B_BCLKX1 CVDD VSS TEST XIO B_RS B_XF B_CLKOUT HMODE HPIRS PPA13 PPA12 VSS DVDD PPA11 PPA10 PPD7 PPA8 PPA0 DVDD PPA9 PPD1 A_INT1 A_NMI IOSTRB A_GPIO2/BIO A_GPIO1 A_RS A_GPIO0 VSS VSS CVDD A_BFSR1 A_BDR1 A_BCLKR1 A_BFSX1 CVDD VSS A_BDX1 A_BCLKX1 A_XF A_CLKOUT HOLDA TCK TMS TDI TRST EMU1/OFF DVDD A_INT0 EMU0 TDO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 NOTES: A. DVDD is the power supply for the I/O pins while CVDD is the power supply for the core CPU. VSS is the ground for both the I/O pins and the core CPU. B. Pin configuration shown for nonmultiplexed mode only. See the pin assignments table for the TMS320VC5421PGE for multiplexed functions of specific pins and for specific pin numbers. Figure 2−1. 144-Pin Low-Profile Flatpack Pin Assignments (PGE − Top View) |
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