TMS320VC5421 datasheet(49/104 Pages) TI1

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Functional Overview

December 1999 − Revised October 2008

SPRS098D

Table 3−14. General-Purpose I/O Control Register Bit Functions

BIT

NO.

BIT

NAME

BIT

VALUE

FUNCTION

TOUT

Timer output disable. Uses GPIO3 as general-purpose I/O.

TOUT

Timer output enable. Overrides DIR3. Timer output is driven on GPIO3 and readable in DAT3.

14-12

Reserved

11−8

GPIO

GPIOn pin is used as an input.

11−8

GPIO

DIRn†

GPIOn pin is used as an output.

ROMEN‡

ROM is mapped out (value at reset if XIO = 0)

ROMEN‡

ROM is mapped in (value at reset if XIO = 1)

CORE

cLEAD core A is selected for XIO REQ bit. DSP subsystem A is tied low internally for this bit.

CORE

SEL

cLEAD core B is selected for XIO REQ bit. DSP subsystem B is tied high internally for this bit.

XIO

EMIF is not available to the cLEAD core determined by the CORE SEL bit.

XIO

GRANT

EMIF is granted to the cLEAD core determined by the CORE SEL bit.

XIO

EMIF is not requested for the cLEAD core indicated by the CORE SEL bit.

XIO

REQ

Request EMIF for the cLEAD core indicated by the CORE SEL bit.

3−0

GPIO

†

GPIOn is driven with a 0 (DIRn = 1). GPIOn is read as 0 (DIRn = 0).

3−0

GPIO

DATn†

GPIOn is driven with a 1 (DIRn = 1). GPIOn is read as 1 (DIRn = 0).

† n = 3, 2, 1, or 0

‡ 1 denotes XIO = 1, 0 denotes XIO = 0

reflects the state of the A_GPIO0 and B_GPIO0 pins (GPIODAT0 input) to enable the applicable on-chip ROM

after reset. Register bits (6:4) are used for XIO arbitration of external memory interface (EMIF) control between

DSP subsystems. The timer out (TOUT) bit is used to multiplex the output of the timer and GPIO3. All GPIO

pins are programmable as an input or output by the direction bit (DIRn). Data is either driven or read from the

data bit field (DATn). DIR3 has no affect when TOUT = 1.

GPIO2 is a special case where the logic level determines the operation of BIO-conditional instructions on the

CPU. GPIO2 is always mapped as a general-purpose I/O, but the BIO function exists when this pin is

configured as an input.

3.9.1 Hardware Timer

The 54x devices feature a 16-bit timing circuit with a 4-bit prescaler. The timer counter decrements by one at

every CLKOUT cycle. Each time the counter decrements to zero, a timer interrupt is generated. The timer can

be stopped, restarted, reset, or disabled by specific status bits. The timer output pulse is driven on GPIO3

when the TOUT bit is set to one in the general-purpose I/O control register. The device must be in HPI mode

(XIO = 0) to drive TOUT on the GPIO3 pin.

3.9.2 Software-Programmable Phase-Locked Loop (PLL)

The clock generator provides clocks to the 5421 device, and consists of a phase-locked loop (PLL) circuit. The

clock generator requires a reference clock input, which must be provided by using an external clock source.

The reference clock input is then divided by two (DIV mode) to generate clocks for the 5421 device. Alternately,

the PLL circuit can be used (PLL mode) to generate the device clock by multiplying the reference clock

frequency by a scale factor, allowing use of a clock source with a lower frequency than that of the CPU. Bypass

(multiply by 1) is the default mode at reset. The PLL is an adaptive circuit that, once synchronized, locks onto

and tracks an input clock signal. When the PLL is initially started, it enters a transitional mode during which

the PLL acquires lock with the input signal. Once the PLL is locked, it continues to track and maintain

synchronization with the input signal. Then, other internal clock circuitry allows the synthesis of new clock

frequencies for use as master clock for the 5421 device. Only subsystem A controls the PLL. Subsystem B

cannot access the PLL registers.

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