TMS320VC5421 datasheet(71/104 Pages) TI1

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Electrical Specifications

December 1999 − Revised October 2008

SPRS098D

5.8

Parallel I/O Interface Timing

5.8.1 Parallel I/O Port Read

The following timing requirements and switching characteristics tables assume testing over recommended

operating conditions with IOSTRB = 0 and H = 0.5tc(CO) (see Figure 5−8).

Table 5−11. Parallel I/O Port Read Timing Requirements

MIN

MAX

UNIT

ta(A)IO

Access time, read data access from address valid†

3H−12

ta(ISTRBL)IO

Access time, read data access from IOSTRB low

2H−11

tsu(D)IOR

Setup time, read data before CLKOUT high

th(D)IOR

Hold time, read data after CLKOUT high

th(ISTRBH-D)R Hold time, read data after IOSTRB high

† Address and IS timings are included in timings referenced as address.

Table 5−12. Parallel I/O Port Read Switching Characteristics

PARAMETER

MIN

MAX

UNIT

td(CLKL-A)

Delay time, CLKOUT low to address valid†

−1

td(CLKH-ISTRBL) Delay time, CLKOUT high to IOSTRB low

td(CLKH-ISTRBH) Delay time, CLKOUT high to IOSTRB high

th(A)IOR

Hold time, address after CLKOUT low†

−1

† Address and IS timings are included in timings referenced as address.

R/W

IOSTRB

PPD[15:0]

PPA[18:0]

CLKOUT

th(A)IOR

td(CLKH−ISTRBH)

th(D)IOR

tsu(D)IOR

ta(A)IO

td(CLKH−ISTRBL)

td(CLKL−A)

ta(ISTRBL)IO

th(ISTRBH−D)R

Figure 5−8. Parallel I/O Port Read (IOSTRB=0)

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