TMS320VC5421 datasheet(64/104 Pages) TI1

64 / 104 page

Electrical Specifications

December 1999 − Revised October 2008

SPRS098D

5.5

Clock Options

The frequency of the reference clock provided at the CLKIN pin can be divided by a factor of two or four to

generate the internal machine cycle. The selection of the clock mode is described in the

software-programmable phase-locked loop (PLL) section.

5.5.1 Divide-By-Two, Divide-By-Four, and Bypass Clock Option (PLL Disabled)

The frequency of the reference clock provided at the CLKIN pin can be divided by a factor of two or four to

generate the internal machine cycle. The selection of the clock mode is described in the

software-programmable phase-locked loop (PLL) section.

The following timing requirements and switching characteristics tables assume testing over recommended

operating conditions and H = 0.5tc(CO) (see Figure 5−2).

Table 5−3. Divide-By-2 and Divide-by-4 Clock Options Timing Requirements

MIN

MAX

UNIT

tc(CI)

Cycle time, CLKIN

†

tf(CI)

Fall time, CLKIN

tr(CI)

Rise time, CLKIN

tw(CIL)

Pulse duration, CLKIN low

tw(CIH) Pulse duration, CLKIN high

† This device utilizes a fully static design and therefore can operate with tc(CI) approaching ∞. The device is characterized at frequencies

approaching 0 Hz.

Table 5−4. Divide-By-2 and Divide-by-4 Clock Options Switching Characteristics

PARAMETER

MIN

TYP

MAX

UNIT

tc(CO)

Cycle time, CLKOUT

2tc(CI)

†

tc(CO)

Cycle time, CLKOUT − bypass mode

2tc(CI)

†

td(CIH-CO)

Delay time, CLKIN high to CLKOUT high/low

tf(CO)

Fall time, CLKOUT

tr(CO)

Rise time, CLKOUT

tw(COL)

Pulse duration, CLKOUT low

H−2

H−1

H+2

tw(COH)

Pulse duration, CLKOUT high

H−2

H−1

H+2

† This device utilizes a fully static design and therefore can operate with tc(CI) approaching ∞. The device is characterized at frequencies

approaching 0 Hz.

tr(CO)

tf(CO)

CLKOUT

CLKIN

tw(COL)

td(CIH-CO)

tf(CI)

tr(CI)

tc(CO)

tc(CI)

tw(COH)

tw(CIH)

tw(CIL)

Figure 5−2. External Divide-by-Two Clock Timing

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