TMS320VC5421 datasheet(39/104 Pages) TI1

39 / 104 page

Functional Overview

December 1999 − Revised October 2008

SPRS098D

Reserved

XIOEN

RIOEN

FSXM

FSRM

CLKXM

CLKRM

R,+0

RW,+0

210

SCLKME

CLKS_STAT

DX_STAT

DR_STAT

FSXP

FSRP

CLKXP

CLKRP

RW,+0

R,+0

RW,+0

Note:

R = Read, W = Write, +0 = Value at reset

Figure 3−8. Pin Control Register (PCR)

The selection of the sample rate generator (SRG) clock input source is made by the combination of the CLKSM

and SCLKME bit values as shown in Table 3−7.

Table 3−7. Sample Rate Generator Clock Source Selection

SCLKME

CLKSM

SRG Clock Source

CLKS (not available as a pin on 5421)

CPU clock

BCLKR pin

BCLKX pin

When either of the bidirectional pins, BCLKR or BCLKX, is configured as the clock input, its output buffer is

automatically disabled. For example, with SCLKME = 1 and CLKSM = 0, the BCLKR pin is configured as the

SRG input. In this case, both the transmitter and receiver circuits can be synchronized to the SRG output by

setting the PCR bits (9:8) for CLKXM = 1 and CLKRM = 1. However, the SRG output is only driven onto the

BCLKX pin because the BCLKR output is automatically disabled.

The McBSP supports independent selection of multiple channels for the transmitter and receiver. When

multiple channels are selected, each frame represents a time-division multiplexed (TDM) data stream. In using

time-division multiplexed data streams, the CPU may only need to process a few of them. Thus, to save

memory and bus bandwidth, multichannel selection allows independent enabling of particular channels for

transmission and reception. Up to a maximum of 128 channels in a bit stream can be enabled or disabled.

The 5421 McBSPs have two working modes that are selected by setting the RMCME and XMCME bits in the

multichannel control registers (MCR1x and MCR2x, respectively). See Figure 3−9 and Figure 3−10. For a

description of the remaining bits, see TMS320C54x DSP Reference Set, Volume 5: Enhanced Peripherals

(literature number SPRU302).

•

In the first mode, when RMCME = 0 and XMCME = 0, there are two partitions (A and B), with each

containing 16 channels as shown in Figure 3−9 and Figure 3−10. This is compatible with the McBSPs

used in the 5420, where only 32-channel selection is enabled (default).

Reserved

XMCME

XPBBLK

XPABLK

XCBLK

XMCM

R,+0

RW,+0

R,+0

RW,+0

Note:

R = Read, W = Write, +0 = Value at reset; x = McBSP 0,1, or 2

Figure 3−9. Multichannel Control Register 2x (MCR2x)

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