TMS320VC5421 datasheet(93/104 Pages) TI1

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Electrical Specifications

December 1999 − Revised October 2008

SPRS098D

Table 5−36. HPI16 Mode Switching Characteristics (Continued)

PARAMETER

UNIT

MAX

MIN

td(HSL-HYL) Delay time, HAS low to HRDY low, read

td(COH−HTX) Delay time, CLKOUT rising edge to HINT change

† HAD stands for HCNTL0, HCNTL1, and HR/W.

‡ HDS refers to either HDS1 or HDS2.

§ DS refers to either HCS or HDS, whichever is controlling the transfer. Refer to the TMS320C54x DSP Reference Set, Volume 5: Enhanced

Peripherals (literature number SPRU302) for information regarding logical operation of the HPI16. These timings are shown assuming that

HDS is the signal controlling the transfer.

¶ HRDY does not go low for other register accesses.

# These timings are for HPI accesses which do not cross from one subsystem to the other. For accesses which do cross from one subsystem

to the other, additional cycles are required. A detailed description of these considerations is provided in the application note Memory Transfers

with TMS320VC5420 and TMS320VC5421 DSPs (literature number SPRA620).

PF Data

Data 1

HRDY

HD[15:0]

HCNTL[1:0]

HR/W

HDS

HAS

HCS

tc(DSH−DSH)

tw(DSH)

tw(DSL)

td(DSL−HDV2)

td(DSH−HYH)†

th(DSH−HDV)R

tv(HYH−HDV)

td(DSL−HDD)

th(HSL−HBV)

tsu(HBV−HSL)

tsu(HSL−DSL)

th(HSL−DSL)

td(DSH−HYL)†

td(HSL−HDV1)

td(HSL−HYL)

† HRDY goes low at these times only after autoincrement reads.

Figure 5−27. Multiplexed Read Timings Using HAS

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