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TMS320VC5421 датащи(PDF) 81 Page - Texas Instruments

номер детали TMS320VC5421
подробное описание детали  Fixed-Point Digital Signal Processor
PDF  104 Pages
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TMS320VC5421 датащи(HTML) 81 Page - Texas Instruments

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Electrical Specifications
81
December 1999 − Revised October 2008
SPRS098D
5.14 Multichannel Buffered Serial Port (McBSP) Timing
5.14.1
McBSP Transmit and Receive Timings
The following timing requirements and switching characteristics tables assume testing over recommended
operating conditions and H = 0.5tc(CO) (see Figure 5−19 and Figure 5−20).
Table 5−21. McBSP T
ransmit and Receive Timing Requirements
MIN
MAX
UNIT
tc(BCKRX)
Cycle time, BCLKR/X
BCLKR/X ext
4H
ns
tw(BCKRX)
Pulse duration, BCLKR/X low or BCLKR/X high
BCLKR/X ext
6
ns
th(BCKRL-BFRH)
Hold time, external BFSR high after BCLKR low
BCLKR int
0
ns
th(BCKRL-BFRH)
Hold time, external BFSR high after BCLKR low
BCLKR ext
4
ns
th(BCKRL-BDRV)
Hold time, BDR valid after BCLKR low
BCLKR int
0
ns
th(BCKRL-BDRV)
Hold time, BDR valid after BCLKR low
BCLKR ext
5
ns
th(BCKXL-BFXH)
Hold time, external BFSX high after BCLKX low
BCLKX int
0
ns
th(BCKXL-BFXH)
Hold time, external BFSX high after BCLKX low
BCLKX ext
4
ns
tsu(BFRH-BCKRL)
Setup time, external BFSR high before BCLKR low
BCLKR int
10
ns
tsu(BFRH-BCKRL)
Setup time, external BFSR high before BCLKR low
BCLKR ext
4
ns
tsu(BDRV-BCKRL)
Setup time, BDR valid before BCLKR low
BCLKR int
10
ns
tsu(BDRV-BCKRL)
Setup time, BDR valid before BCLKR low
BCLKR ext
3
ns
tsu(BFXH-BCKXL)
Setup time, external BFSX high before BCLKX low
BCLKX int
10
ns
tsu(BFXH-BCKXL)
Setup time, external BFSX high before BCLKX low
BCLKX ext
6
ns
tr(BCKRX)
Rise time, BCLKR/X
BCLKR/X ext
8
ns
tf(BCKRX)
Fall time, BCLKR/X
BCLKR/X ext
8
ns
† Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are
also inverted.



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