TMS320VC5421 datasheet(75/104 Pages) TI1

75 / 104 page

Electrical Specifications

December 1999 − Revised October 2008

SPRS098D

5.10 Reset, BIO, Interrupt, and MP/MC Timings

The following timing requirements table assumes testing over recommended operating conditions and

H = 0.5tc(CO) (see Figure 5−12, Figure 5−13, and Figure 5−14).

Table 5−15. Reset, BIO, Interrupt, and MP/MC Timing Requirements

MIN

MAX

UNIT

th(RS)

Hold time, RS after CLKOUT low

th(BIO)

Hold time, BIO after CLKOUT low

th(INT)

Hold time, INTn, NMI, after CLKOUT low†

tw(RSL)

Pulse duration, RS low‡§

4H+5

tw(BIO)A

Pulse duration, BIO low, asynchronous†

tw(INTH)A

Pulse duration, INTn, NMI high (asynchronous)†

tw(INTL)A

Pulse duration, INTn, NMI low (asynchronous)†

tw(INTL)WKP Pulse duration, INTn, NMI low for IDLE2/IDLE3 wakeup†

tw(XIO)

Pulse duration, XIO switched

ten(XIO)

Enable time, after XIO switched

4H+10

tsu(RS)

Setup time, RS before CLKIN low§

tsu(BIO)

Setup time, BIO before CLKOUT low

tsu(INT)

Setup time, INTn, NMI, RS before CLKOUT low

† The external interrupts (INT0−INT1, NMI) are synchronized to the core CPU by way of a two flip-flop synchronizer which samples these inputs

with consecutive falling edges of CLKOUT. The input to the interrupt pins is required to represent a 1-0-0 sequence at the timing that is

corresponding to a three-CLKOUT sampling sequence.

‡ If the PLL mode is selected, then at power-on sequence, or at wakeup from IDLE3, RS must be held low for at least 50 µs to ensure synchronization

and lock-in of the PLL.

§ RS can cause a change in clock frequency, changing the value of H (see the software-programmable phase-locked loop (PLL) section).

BIO

CLKOUT

A_RS, B_RS,

INTn, NMI

CLKIN

th(BIO)

th(RS)

tsu(INT)

tw(BIO)A

tsu(BIO)

tw(RSL)

tsu(RS)

Figure 5−12. Reset and BIO Timings

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